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2021-11-05cmd/{asm,compile,internal/obj}: add "maymorestack" supportAustin Clements
This adds a debugging hook for optionally calling a "maymorestack" function in the prologue of any function that might call morestack (whether it does at run time or not). The maymorestack function will let us improve lock checking and add debugging modes that stress function preemption and stack growth. Passes toolstash-check -all (except on js/wasm, where toolstash appears to be broken) Fixes #48297. Change-Id: I27197947482b329af75dafb9971fc0d3a52eaf31 Reviewed-on: https://go-review.googlesource.com/c/go/+/359795 Trust: Austin Clements <austin@google.com> Run-TryBot: Austin Clements <austin@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-11-03cmd/asm,cmd/compile,runtime: stop using X3 (aka GP) on riscv64Joel Sing
The X3 (aka GP) register will potentially be loaded with the __global_pointer$ symbol during program start up (usually by the dynamic linker). As such, non-Go code may depend on the contents of GP and calculate offsets based on it, including code called via cgo and signal handlers installed by non-Go code. As such, stop using the X3 register so that there are fewer issues interacting between Go and non-Go code. While here remove the X4 (TP) name from the assembler such that any references must use the 'TP' name. This should reduce the likelihood of accidental use (like we do for the 'g' register). The same applies for X3 (GP) when the -shared flag is given. Updates #47100 Change-Id: I72e82b5ca3f80c46a781781345ca0432a4111b74 Reviewed-on: https://go-review.googlesource.com/c/go/+/351859 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-10-26cmd/internal/obj/ppc64: fix usage of CR bit argumentsPaul E. Murphy
CR bits and CR fields should be treated separately. Some instructions modify an entire CR, a CR field, or a single CR bit. Add a new argument class for CR bits, and teach the assembler the recognize them as names like CR0LT or CR2SO, and update the CR bit logic instructions to use them. They will no longer accept register field (CRn) type arguments. Fixes #46422 Change-Id: Iaba127d88abada0c2a49b8d3b07a976180565ae4 Reviewed-on: https://go-review.googlesource.com/c/go/+/357774 Run-TryBot: Paul Murphy <murp@ibm.com> Trust: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-10-11cmd/internal/obj/ppc64: fix mtocrf, cleanup other CR opsPaul E. Murphy
Fix "MOVW CRx, Rx" and "MOVFL Rx, constant", The FXM field was not encoded correctly. Generate mtocrf instead of mtcrf when a CRx argument is used. This form is much faster. Simplify several conditional statements which test if the register argument is REG_CR or one of REG_CRx if the tested argument is known to be matched as C_CREG. Likewise, a4 is (the From3 arg) is always TYPE_NONE in the existing optab entries for type_ 69. Change-Id: I3a4749b1cbfdfab6a2616586ae59e932e01dae50 Reviewed-on: https://go-review.googlesource.com/c/go/+/352789 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
2021-10-08cmd/internal/obj: rename MOVBE{LL,QQ,WW} to just MOVBE{L,Q,W}Matthew Dempsky
The double suffix doesn't seem to serve any purpose, and we can keep the old spelling as a backwards compatible alias in cmd/asm. Change-Id: I3f01fc7249fb093ac1b25bd75c1cb9f39b8f62a9 Reviewed-on: https://go-review.googlesource.com/c/go/+/354700 Run-TryBot: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Trust: Matthew Dempsky <mdempsky@google.com>
2021-10-02cmd/internal/obj/riscv,cmd/link/internal/riscv64: add call trampolines for ↵Joel Sing
riscv64 CALL and JMP on riscv64 are currently implemented as an AUIPC+JALR pair. This means that every call requires two instructions and makes use of the REG_TMP register, even when the symbol would be directly reachable via a single JAL instruction. Add support for call trampolines - CALL and JMP are now implemented as a single JAL instruction, with the linker generating trampolines in the case where the symbol is not reachable (more than +/-1MiB from the JAL instruction), is an unknown symbol or does not yet have an address assigned. Each trampoline contains an AUIPC+JALR pair, which the relocation is applied to. Due to the limited reachability of the JAL instruction, combined with the way that the Go linker currently assigns symbol addresses, there are cases where a call is to a symbol that has no address currently assigned. In this situation we have to assume that a trampoline will be required, however we can patch this up during relocation, potentially calling directly instead. This means that we will end up with trampolines that are unused. In the case of the Go binary, there are around 3,500 trampolines of which approximately 2,300 are unused (around 9200 bytes of machine instructions). Overall, this removes over 72,000 AUIPC instructions from the Go binary. Change-Id: I2d9ecfb85dfc285c7729a3cd0b3a77b6f6c98be0 Reviewed-on: https://go-review.googlesource.com/c/go/+/345051 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-30cmd/asm: add error check for move constant instructions on arm64fanzha02
The current Go assembler encodes "MOVK $(0<<16|32|48), Rd" as the same binary with "MOVK $0, Rd", but for arm64 move constant instructions MOVK, MOVN and MOVZ, "op $0, Rd" and "op $(0<<16|32|48), Rd" have different semantics. In order not to change the way the assembler frontend parses constants, this patch adds a check for the zero shifts. Change-Id: Ia844c419ce49f63605b549e3a2e98d9075dd1cf1 Reviewed-on: https://go-review.googlesource.com/c/go/+/275812 Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-14cmd/internal/obj/ppc64: allow VR register arguments to VS registersPaul E. Murphy
Likewise, reorder register numbers such that extended mnemonics which use FPR arguments can be transparently encoded as a VSR argument for the move to/from VSR class of instructions. Specifically, ensure the following holds for all FPx and VRx constants: FPRx & 63 == x, and VRx & 63 == x + 32. This simplifies encoding machine instructions, and likewise helps ppc64 assembly writers to avoid hokey workarounds when switching from vector to vector-scalar register notation. Notably, many VSX instructions are limited to vector operands due to encoding restrictions. Secondly, this explicitly rejects dubious usages of the m[tf]vsr family of instructions which had previously been accepted. * Reject two GPR arguments for non-MTVSRDD opcodes. These have no defined behavior today, and may set RFU bits. e.g MTVSRD R1, R2, VS1 * Reject FPR destinations for MTVSRDD, and only accept with two GPR arguments. This copies two GPR values into either half of a VSR. e.g MTVSRDD R1, R2, F1 MTVSRDD R1, F1 Change-Id: If13dd88c3791d1892dbd18ef0e34675a5285fff9 Reviewed-on: https://go-review.googlesource.com/c/go/+/342929 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-10cmd/compile: add support for Abs and Copysign intrinsics on riscv64Michael Munday
Also, add the FABSS and FABSD pseudo instructions to the assembler. The compiler could use FSGNJX[SD] directly but there doesn't seem to be much advantage to doing so and the pseudo instructions are easier to understand. Change-Id: Ie8825b8aa8773c69cc4f07a32ef04abf4061d80d Reviewed-on: https://go-review.googlesource.com/c/go/+/348989 Trust: Michael Munday <mike.munday@lowrisc.org> Run-TryBot: Michael Munday <mike.munday@lowrisc.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au>
2021-09-09cmd/internal/obj/arm64: add checks for incorrect use of REGTMP registerfanzha02
The current assembler uses REGTMP as a temporary destination register, when optimizing one instruction into a multi-instruction sequence. But in some cases, when the source register is REGTMP, this behavior is incorrect. For example: ADD $0x1234567, R27, R3 The current assembler encodes it into MOVD $17767, R27 MOVK $(291<<16), R27 ADD R27, R27, R3 It is illegal to overwrite R27. This CL adds the related checks. Add test cases. Change-Id: I0af373d9fd23d8f067c093778dd4cc76748faf38 Reviewed-on: https://go-review.googlesource.com/c/go/+/344689 Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: fannie zhang <Fannie.Zhang@arm.com>
2021-09-08cmd/internal/obj/riscv: simplify rewriteMOVJoel Sing
Rewrite and simplify the rewriteMOV function in preparation for eliminating it entirely. Improve some error messages in the process. Change-Id: Id9a77be5174d46cc23651930c2e9068ee6555690 Reviewed-on: https://go-review.googlesource.com/c/go/+/344458 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-09-04cmd/internal/obj/riscv: improve code generation for loading of constantsJoel Sing
Loading of constants that are 12 bits or smaller is currently performed using a single ADDIW instruction, while constants between 13 bits and 32 bits are loaded using a LUI+ADDIW pair. Instead, use a single ADDI instruction for the 12 bits or smaller case - this translates to the LI pseudo-instruction, making objdump more readable and giving: 11c7c: fff00293 li t0,-1 11c80: 00000313 li t1,0 Rather than: 11c7c: fff0029b addiw t0,zero,-1 11c80: 0000031b sext.w t1,zero In the case where a constant exceeds 12 bits, an LUI instruction is required, however if the lower 12 bits are zero, the ADDIW instruction can be omitted. The same applies to the case where immediate splitting is performed for other immediate instructions. This removes around 900 instructions from the Go binary. Change-Id: Id6c77774b3b429fa525da018a6926b85df838a2f Reviewed-on: https://go-review.googlesource.com/c/go/+/344457 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04cmd/internal/obj/riscv: avoid obj.Prog rewriting for immediate splittingJoel Sing
Rather than rewriting the obj.Prog for a immediate instructions that need splitting, generate the appropriate machine instruction sequence directly. Change-Id: Ie90f0e2a98f97a29281e445c4c3b0c47b793ef4d Reviewed-on: https://go-review.googlesource.com/c/go/+/344453 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04cmd/internal/obj/riscv: avoid obj.Prog rewriting for memory loadsJoel Sing
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting a memory to register load, generate the appropriate machine instruction sequence directly. Change-Id: I4c7292ba00f576ec71d4842b6ff27a8ce6db0650 Reviewed-on: https://go-review.googlesource.com/c/go/+/344454 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04cmd/internal/obj/riscv: avoid obj.Prog rewriting for constant loadsJoel Sing
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting a constant to register load, generate the appropriate machine instruction sequence directly. Change-Id: I38e62f282b39be2a0a241f32280d306558d49b44 Reviewed-on: https://go-review.googlesource.com/c/go/+/344450 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-09-01cmd/{asm,compile}: add fused multiply-add support on riscv64Michael Munday
Add support to the assembler for F[N]M{ADD,SUB}[SD] instructions. Argument order is: OP RS1, RS2, RS3, RD Also, add support for the FMA intrinsic to the compiler. Automatic FMA matching is left to a future CL. Change-Id: I47166c7393b2ab6bfc2e42aa8c1a8997c3a071b3 Reviewed-on: https://go-review.googlesource.com/c/go/+/293030 Trust: Michael Munday <mike.munday@lowrisc.org> Run-TryBot: Michael Munday <mike.munday@lowrisc.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au>
2021-09-01cmd/asm: adjust riscv64 test data to avoid churnJoel Sing
Rather than jumping and branching to a label (the offset for which changes when instructions are added or removed), use PC-relative offsets. This reduces unnecessary churn in the instruction encodings. Change-Id: I6816ce939eeabdf828039f59f4f29260eb1ac8da Reviewed-on: https://go-review.googlesource.com/c/go/+/344449 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Michael Munday <mike.munday@lowrisc.org>
2021-09-01cmd/asm,cmd/internal/obj/riscv: add more error tests for riscv64 assemblyJoel Sing
Add more error tests for riscv64 assembly. Also avoid a panic when one of these error conditions is hit. Change-Id: If5d913894facbd67f7d014eab745da77c8c66ab0 Reviewed-on: https://go-review.googlesource.com/c/go/+/344228 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Meng Zhuo <mzh@golangcn.org>
2021-08-20cmd/asm/internal/arch: adds the missing type check for arm64 SXTB extensioneric fang
Operands of memory type do not support SXTB extension. This CL adds this missing check. Change-Id: I1fa438dd314fc8aeb889637079cc67b538e83a89 Reviewed-on: https://go-review.googlesource.com/c/go/+/342769 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Michael Knyszek <mknyszek@google.com>
2021-08-20cmd/internal/obj/arm64: disable the pre and post index formats for pseudo ↵eric fang
registers When using the FP or SP pseudo-register to load or store, pre-index and post-index formats are not supported because the RSP and pseudo registers are not allowed to be modified in this way. This CL deletes the related entries in optab and adds a few test cases. Change-Id: Ie30d27d0e7b959242f0e6298b950489669d07989 Reviewed-on: https://go-review.googlesource.com/c/go/+/342770 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> Trust: Michael Knyszek <mknyszek@google.com>
2021-08-18cmd/internal/obj/arm64: don't use REGTMP when moving C_AACON2 to a registereric fang
MOVD $C_AACON2(Rf), Rt is encoded as ADD $C_AACON2_high_12_bits, Rf, REGTMP + ADD $C_AACON2_low_12_bits, REGTMP, Rt. Actually REGTMP is not necessary here, we can use Rt directly, so it becomes ADD $C_AACON2_high_12_bits, Rf, Rt + ADD $C_AACON2_low_12_bits, Rt, Rt. Change-Id: I90b7718b5fb0ab9f3ea28511f42946a6bdccfef3 Reviewed-on: https://go-review.googlesource.com/c/go/+/329751 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com>
2021-08-18cmd/internal/obj/arm64: fix the encoding error when operating with ZReric fang
Some arm64 instructions accept ZR as its destination register, such as MOVD, AND, ADD etc. although it doesn't seem to make much sense, but we should make sure the encoding is correct. However there exists some encoding mistakes in the current assembler, they are: 1, 'MOVD $1, ZR' is incorrectly encoded as 'MOVD $1, ZR' + '0x00000000'. 2, 'AND $1, R2, ZR' is incorrectly encoded as 'MOVD $1, R27' + 'AND R27, R2, ZR' + '0x00000000'. 3, 'AND $1, ZR' is incorrectly encoded as 'AND $1, ZR, RSP'. Obviously the first two encoding errors can cause SIGILL, and the third one will rewrite RSP. At the same time, I found some weird encodings but they don't cause errors. 4, 'MOVD $0x0001000100010001, ZR' is encoded as 'MOVW $1, ZR' + 'MOVKW $(1<<16), ZR'. 5, 'AND $0x0001000100010001, R2, ZR' is encoded as 'MOVD $1, R27' + 'MOVK $(1<<16), R27' + 'MOVK $(1<<32), R27'. Some of these issues also apply to 32-bit versions of these instructions. These problems are not very complicated, and are basically caused by the improper adaptation of the class of the constant to the entry in the optab. But the relationship between these constant classes is a bit complicated, so I don't know how to deal with issue 4 and 5, because they won't cause errors, so this CL didn't deal with them. This CL fixed the first three issues. Issue 1: before: 'MOVD $1, ZR' => 'MOVD $1, ZR' + '0x00000000'. after: 'MOVD $1, ZR' => 'MOVD $1, ZR'. Issue 2: before: 'AND $1, R2, ZR' => 'MOVD $1, R27' + 'AND R27, R2, ZR' + '0x00000000'. after: 'AND $1, R2, ZR' => 'ORR $1, ZR, R27' + 'AND R27, R2, ZR'. Issue 3: before: 'AND $1, ZR' => 'AND $1, ZR, RSP'. after: 'AND $1, ZR' => 'ORR $1, ZR, R27' + 'AND R27, ZR, ZR'. Change-Id: I3c889079229f847b863ad56c88966be12d947202 Reviewed-on: https://go-review.googlesource.com/c/go/+/329750 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-06-29cmd/internal/obj/arm64: fix an encoding error of CMPW instructioneric fang
For arm64 CMP, ADD and other similar extended register instructions, if there is no extension, the default extion is LSL<<0, but the default encoding value (the value of 'option' field) of 32-bit instruction and 64-bit instruction is different, 32-bit is 2 and 64-bit is 3. But the current assembler incorrectly encodes the value of 32-bit instruction to 3. This CL fixes this error. Change-Id: I0e09af2c9c5047a4ed2db7d1183290283db9c31c Reviewed-on: https://go-review.googlesource.com/c/go/+/329749 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Trust: Dmitri Shuralyov <dmitshur@golang.org>
2021-06-16cmd/asm: restore supporting of *1 scaling on ARM64Cherry Mui
On ARM64, instruction like "MOVD (R1)(R2*1), R3" is accepted and assembles correctly with Go 1.16, but errors out on tip with "arm64 doesn't support scaled register format", since CL 289589. "MOVD (R1)(R2), R3" is the preferred form. But the *1 form works before and assembles correctly. Keep supporting it. Fixes #46766. Change-Id: I0f7fd71fa87ea698919a936b6c68aa5a91afd486 Reviewed-on: https://go-review.googlesource.com/c/go/+/328229 Trust: Cherry Mui <cherryyz@google.com> Trust: Cuong Manh Le <cuong.manhle.vn@gmail.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: eric fang <eric.fang@arm.com>
2021-05-14cmd/internal/obj/arm64: disable AL and NV for some condition operation ↵eric fang
instructions According to the armv8-a reference manual, conditions AL and NV are not allowed for instructions CINC, CINV, CNEG, CSET and CSETM. This CL adds this check and the corresponding test cases. Change-Id: Icb496b7b13a353f41491f2de4d939a5cd88abb04 Reviewed-on: https://go-review.googlesource.com/c/go/+/317912 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-05-10runtime/cgo,cmd/internal/obj/ppc64: fix signals with cgoLynn Boger
Recently some tsan tests were enabled on ppc64le which had not been enabled before. This resulted in failures on systems with tsan available, and while debugging it was determined that there were other issues related to the use of signals with cgo. Signals were not being forwarded within programs linked against libtsan because the nocgo sigaction was being called for ppc64le with or without cgo. Adding callCgoSigaction and calling that allows signals to be registered so that signal forwarding works. For linux-ppc64 and aix-ppc64, this won't change. On linux-ppc64 there is no cgo. I can't test aix-ppc64 so those owners can enable it if they want. In reviewing comments about sigtramp in sys_linux_arm64 it was noted that a previous issue in arm64 due to missing callee save registers could also be a problem on ppc64x, so code was added to save and restore those. Also, the use of R31 as a temp register in some cases caused an issue since it is a nonvolatile register in C and was being clobbered in cases where the C code expected it to be valid. The code sequences to load these addresses were changed to avoid the use of R31 when loading such an address. To get around a vet error, the stubs_ppc64x.go file in runtime was split into stubs_ppc64.go and stubs_ppc64le.go. Updates #45040 Change-Id: Ia4ecff950613cbe1b89471790b1d3819d5b5cfb9 Reviewed-on: https://go-review.googlesource.com/c/go/+/306369 Trust: Lynn Boger <laboger@linux.vnet.ibm.com> Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org>
2021-04-28cmd/asm: add check for register and shift/extension combination on arm64eric fang
The current code lacks a check on whether the register and shift/extension combination is valid, for example the follow instructions also compiles. ADD F1<<1, R1, R3 ADD V1<<1, R1, R3 MOVW (R9)(F8.SXTW<<2), R19 VST1 R4.D[1], (R0) Actually only general registers can perform shift operations, and element and arrangement extensions are only applicable to vector registers. This CL adds a check for the register and shift/extension combination on arm64. Change-Id: I93dd9343e92a66899cba8eaf4e0ac5430e94692b Reviewed-on: https://go-review.googlesource.com/c/go/+/312571 Trust: eric fang <eric.fang@arm.com> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-04-28cmd/internal/obj/arm64: fix the wrong error message of out-of-range checkingeric fang
The error message of checking whether the offset value of load/store instruction is out of range is wrong. The right range is [-256, 255], not [-255, 254]. The CL fixes it. Change-Id: Ia342957f1f6bcec65eceb45944221d3972641bed Reviewed-on: https://go-review.googlesource.com/c/go/+/313891 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com>
2021-04-27cmd/internal/obj: refactor ppc64 address relocation code generationPaul E. Murphy
The code for generating a long constant versus generating an address (either via a relocation, or known offset) should be handled in the same place. Resolve this by classifying memory arguments as C_LACON (a long address constant) instead of C_LCON (a long constant). Likewise, reorder AMOVD/AMOVW optab entries to keep similar classifications near each other. An extra optab entry for DWORD is also added to continue handling C_LACON arguments correctly. Change-Id: I5ce28400492a071f615125a9b8d260826f1600d7 Reviewed-on: https://go-review.googlesource.com/c/go/+/312296 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org> Trust: Carlos Eduardo Seo <carlos.seo@linaro.org>
2021-04-23cmd/asm, cmd/link: use full objabi headerRuss Cox
The cmd/link check of the objabi header was a bit lax because historically the assembler has not included the full version string. And the assembler didn't do that because it didn't have access to it: that was buried inside the compiler. But now that we have cmd/internal/objabi, all the tools have full access to the expected string, and they can use it, which simplifies the cmd/link consistency check. Do that. Change-Id: I33bd2f9d36c373cc3c32ff02ec6368365088b011 Reviewed-on: https://go-review.googlesource.com/c/go/+/312030 Trust: Russ Cox <rsc@golang.org> Run-TryBot: Russ Cox <rsc@golang.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-04-22cmd/asm: fix RLDCR const1,reg,const2,reg on ppc64Paul E. Murphy
The extended opcode field (XO) is generated incorrectly. OPVCC assumes an X-form like layout for the XO field. MD-form insns also have an XO field, but it is both smaller and in a different bit position. This hasn't been noticed since const1 == 0 matches as a register argument instead of a constant, thus it is unlikely anyone has attempted to assemble this instruction with a non-zero shift argument. Likewise, update all other MD-form instructions using OPVCC to use the new OPMD function. Change-Id: Id81fa2727fb701431911a05492c2038415ad0a4d Reviewed-on: https://go-review.googlesource.com/c/go/+/310851 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org>
2021-04-22cmd/internal/obj/arm64: fix the wrong ROR operator of some instructionseric fang
Instructions such as ADD, SUB, CMP do not support ROR shift operations, but we have not checked this at present. This CL adds this check. Change-Id: Icac461f61ad6ddb60886a59ba34dddd29df1cc0f Reviewed-on: https://go-review.googlesource.com/c/go/+/310035 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-04-16internal/buildcfg: move build configuration out of cmd/internal/objabiRuss Cox
The go/build package needs access to this configuration, so move it into a new package available to the standard library. Change-Id: I868a94148b52350c76116451f4ad9191246adcff Reviewed-on: https://go-review.googlesource.com/c/go/+/310731 Trust: Russ Cox <rsc@golang.org> Run-TryBot: Russ Cox <rsc@golang.org> Reviewed-by: Austin Clements <austin@google.com> Reviewed-by: Jay Conrod <jayconrod@google.com>
2021-04-15cmd/internal/obj: consolidate AMOVW and AMOVWZ optab entriesPaul E. Murphy
This requires consolidating the register move operations into a single case entry in asmout. These moves are also used to sign/zero-extend register values. Combine the three asmout cases for register moves. This allows AMOVWZ and AMOVW to be handled with the same optab entries. Likewise, remove the diagnostic error for non-zero constant loads into R0 using the register move operations, it is not possible to match this asmout case with a non-zero constant. Finally, fix the load constant 0 via "MOV[BHW]{,Z} $0, Rx". These now generate "li Rx, $0" instead of a zero/sign-extend of the contents of R0. Change-Id: Ia4a263661582f10feda27ee21cb121e05ea931dc Reviewed-on: https://go-review.googlesource.com/c/go/+/308190 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org> Trust: Carlos Eduardo Seo <carlos.seo@linaro.org>
2021-04-15cmd/internal/obj/arm64: fix the wrong sp dst register of ADDS/SUBS instructionseric fang
According the armv8-a specification, the destination register of the ADDS/ADDSW/ SUBS/SUBSW instructions can not be RSP, the current implementation does not check this and encodes this wrong instruction format as a CMN instruction. This CL adds a check and test cases for this situation. Change-Id: I92cc2f8e17dbda70f0dce8fddf1ca6d5d7730589 Reviewed-on: https://go-review.googlesource.com/c/go/+/309989 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-04-14cmd/asm: require NOSPLIT for ABIInternal asm functionsThan McIntosh
Change the assembler to enforce the requirement that ABIInternal functions need to be NOSPLIT. At the moment all of the assembly routines in the runtime that are defined as ABIInternal also happen to be NOSPLIT, but this CL makes it mandatory. Updates #40724. Change-Id: Ief80d22de1782edb44b798fcde9aab8a93548722 Reviewed-on: https://go-review.googlesource.com/c/go/+/309789 Trust: Than McIntosh <thanm@google.com> Run-TryBot: Than McIntosh <thanm@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Austin Clements <austin@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-04-08internal/goexperiment,cmd: consolidate GOEXPERIMENTs into a new packageAustin Clements
Currently there's knowledge about the list of GOEXPERIMENTs in a few different places. This CL introduces a new package and consolidates the list into one place: the internal/goexperiment.Flags struct type. This package gives us a central place to document the experiments as well as the GOEXPERIMENT environment variable itself. It will also give us a place to put built-time constants derived from the enabled experiments. Now the objabi package constructs experiment names by reflecting over this struct type rather than having a separate list of these names (this is similar to how the compiler handles command-line flags and debug options). We also expose a better-typed API to the toolchain for propagating enabled experiments. Change-Id: I06e026712b59fe2bd7cd11a869aedb48ffe5a4b7 Reviewed-on: https://go-review.googlesource.com/c/go/+/307817 Trust: Austin Clements <austin@google.com> Run-TryBot: Austin Clements <austin@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Matthew Dempsky <mdempsky@google.com>
2021-04-08cmd/asm,runtime: reduce spellings of GOEXPERIMENTsAustin Clements
Currently, the objabi.Experiment fields use Go-standard CamelCase, the GOEXPERIMENT environment variable flags and build tags use all lowercase, and the asm macros use upper-case with underscores. This CL makes asm use the lowercase names for macros so there is one less spelling, e.g., GOEXPERIMENT_regabiargs. This also makes them consistent with the GOOS_* and GOARCH_* macros, which also use lower case. Change-Id: I305cd89af5e8cd1a89cc148746c034bcfd76db3c Reviewed-on: https://go-review.googlesource.com/c/go/+/307816 Trust: Austin Clements <austin@google.com> Run-TryBot: Austin Clements <austin@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> Reviewed-by: Matthew Dempsky <mdempsky@google.com>
2021-03-19cmd/asm: complete the support for VDUP on arm64fanzha02
"VMOV Vn.<T>[index], Vn" is equivalent to "VDUP Vn.<T>[index], Vn", and the latter has a higher priority in the disassembler than the former. But the assembler doesn't support to encode this combination of VDUP, this leads to an inconsistency between assembler and disassembler. For example, if we assemble "VMOV V20.S[0], V20" to hex then decode it, we'll get "VDUP V20.S[0], V20". VMOV V20.S[0], V20 -> 9406045e -> VDUP V20.S[0], V20 -> error But we cannot assemble this VDUP again. Similar reason for "VDUP Rn, Vd.<T>". This CL completes the support for VDUP. This patch is a copy of CL 276092. Co-authored-by: JunchenLi <junchen.li@arm.com> Change-Id: I8f8d86cf1911d5b16bb40d189f1dc34b24416aaf Reviewed-on: https://go-review.googlesource.com/c/go/+/302929 Trust: fannie zhang <Fannie.Zhang@arm.com> Run-TryBot: fannie zhang <Fannie.Zhang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-18all: explode GOEXPERIMENT=regabi into 5 sub-experimentsAustin Clements
This separates GOEXPERIMENT=regabi into five sub-experiments: regabiwrappers, regabig, regabireflect, regabidefer, and regabiargs. Setting GOEXPERIMENT=regabi now implies the working subset of these (currently, regabiwrappers, regabig, and regabireflect). This simplifies testing, helps derisk the register ABI project, and will also help with performance comparisons. This replaces the -abiwrap flag to the compiler and linker with the regabiwrappers experiment. As part of this, regabiargs now enables registers for all calls in the compiler. Previously, this was statically disabled in regabiEnabledForAllCompilation, but now that we can control it independently, this isn't necessary. For #40724. Change-Id: I5171e60cda6789031f2ef034cc2e7c5d62459122 Reviewed-on: https://go-review.googlesource.com/c/go/+/302070 Trust: Austin Clements <austin@google.com> Run-TryBot: Austin Clements <austin@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
2021-03-18cmd/compile,cmd/internal/obj/riscv: load >32-bit constants from memory for ↵Joel Sing
riscv64 Follow what MIPS does and load >32-bit constants from memory using two instructions, rather than generating a four to six instruction sequence. This removes more than 2,500 instructions from the Go binary. This also makes it possible to load >32-bit constants via a single assembly instruction, if required. Change-Id: Ie679a0754071e6d8c52fe0d027f00eb241b3a758 Reviewed-on: https://go-review.googlesource.com/c/go/+/302609 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-16cmd/asm: when dynamic linking, reject code that uses a clobbered R15Keith Randall
The assember uses R15 as scratch space when assembling global variable references in dynamically linked code. If the assembly code uses the clobbered value of R15, report an error. The user is probably expecting some other value in that register. Getting rid of the R15 use isn't very practical (we could save a register to a field in the G maybe, but that gets cumbersome). Fixes #43661 Change-Id: I43f848a3d8b8a28931ec733386b85e6e9a42d8ff Reviewed-on: https://go-review.googlesource.com/c/go/+/283474 Trust: Keith Randall <khr@golang.org> Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-16cmd/asm: add rotr/drotr for mips64Meng Zhuo
This CL encodes: ROTR rd, rt, sa ROTRV rd, rt, rs => ROTR (SCON|REG), (REG,)? REG DROTR rd, rt, sa DROTR32 rd, rt, sa DROTRV rd, rt, rs => ROTRV (SCON|REG), (REG,)? REG Note: ROTRV will handle const over 32 Ref: The MIPS64® Instruction Set Reference Manual Revision 6.05 Change-Id: Ibe69f999b83eb43843d088cf1ac5a13c995269a5 Reviewed-on: https://go-review.googlesource.com/c/go/+/280114 Trust: Meng Zhuo <mzh@golangcn.org> Run-TryBot: Meng Zhuo <mzh@golangcn.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-12cmd/internal/obj/arm64: add support for op(extended register) with RSP argumentsfanzha02
Refer to ARM reference manual, like add(extended register) instructions, the extension is encoded in the "option" field. If "Rd" or "Rn" is RSP and "option" is "010" then LSL is preferred. Therefore, the instrution "add Rm<<imm, RSP, RSP" or "add Rm<<imm RSP" is valid and can be encoded as add(extended register) instruction. But the current assembler can not handle like "op R1<<1, RSP, RSP" instructions, this patch adds the support. Because MVN(extended register) does not exist, remove it. Add test cases. Change-Id: I968749d75c6b93a4f297b39c73cc292e6b1035ad Reviewed-on: https://go-review.googlesource.com/c/go/+/284900 Trust: fannie zhang <Fannie.Zhang@arm.com> Run-TryBot: fannie zhang <Fannie.Zhang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-11cmd: move GOEXPERIMENT knob from make.bash to cmd/goMatthew Dempsky
This CL changes GOEXPERIMENT to act like other GO[CONFIG] environment variables. Namely, that it can be set at make.bash time to provide a default value used by the toolchain, but then can be manually set when running either cmd/go or the individual tools (compiler, assembler, linker). For example, it's now possible to test rsc.io/tmp/fieldtrack by simply running: GOEXPERIMENT=fieldtrack go test -gcflags=-l rsc.io/tmp/fieldtrack \ -ldflags=-k=rsc.io/tmp/fieldtrack.tracked without needing to re-run make.bash. (-gcflags=-l is needed because the compiler's inlining abilities have improved, so calling a function with a for loop is no longer sufficient to suppress inlining.) Fixes #42681. Change-Id: I2cf8995d5d0d05f6785a2ee1d3b54b2cfb3331ca Reviewed-on: https://go-review.googlesource.com/c/go/+/300991 Trust: Matthew Dempsky <mdempsky@google.com> Run-TryBot: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Bryan C. Mills <bcmills@google.com>
2021-03-09cmd/asm,cmd/compile: support 5 operand RLWNM/RLWMI on ppc64Paul E. Murphy
These instructions are actually 5 argument opcodes as specified by the ISA. Prior to this patch, the MB and ME arguments were merged into a single bitmask operand to workaround the limitations of the ppc64 assembler backend. This limitation no longer exists. Thus, we can pass operands for these opcodes without having to merge the MB and ME arguments in the assembler frontend or compiler backend. Likewise, support for 4 operand variants is unchanged. Change-Id: Ib086774f3581edeaadfd2190d652aaaa8a90daeb Reviewed-on: https://go-review.googlesource.com/c/go/+/298750 Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org> Trust: Carlos Eduardo Seo <carlos.seo@linaro.org>
2021-03-04cmd/asm: disable scaled register format for arm64eric fang
Arm64 doesn't have scaled register format, such as (R1*2), (R1)(R2*3), but currently the assembler doesn't report an error for such kind of instruction operand format. This CL disables the scaled register operand format for arm64 and reports an error if this kind of instruction format is seen. With this CL, the assembler won't print (R1)(R2) as (R1)(R2*1), so that we can make the assembly test simpler. Change-Id: I6d7569065597215be4c767032a63648d2ad16fed Reviewed-on: https://go-review.googlesource.com/c/go/+/289589 Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-04cmd/internal/obj/asm64: add support for moving BITCON to RSPeric fang
Constant of BITCON type can be moved into RSP by MOVD or MOVW instructions directly, this CL enables this format of these two instructions. For 32-bit ADDWop instructions with constant, rewrite the high 32-bit to be a repetition of the low 32-bit, just as ANDWop instructions do, so that we can optimize ADDW $bitcon, Rn, Rt as: MOVW $bitcon, Rtmp ADDW Rtmp, Rn, Rt The original code is: MOVZ $bitcon_low, Rtmp MOVK $bitcon_high,Rtmp ADDW Rtmp, Rn, Rt Change-Id: I30e71972bcfd6470a8b6e6ffbacaee79d523805a Reviewed-on: https://go-review.googlesource.com/c/go/+/289649 Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-04cmd/asm: add arm64 instructions VUMAX and VUMINeric fang
This CL adds support for arm64 fp&simd instructions VUMAX and VUMIN. Fixes #42326 Change-Id: I3757ba165dc31ce1ce70f3b06a9e5b94c14d2ab9 Reviewed-on: https://go-review.googlesource.com/c/go/+/271497 Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-04cmd/asm: add 128-bit FLDPQ and FSTPQ instructions for arm64eric fang
This CL adds assembly support for 128-bit FLDPQ and FSTPQ instructions. This CL also deletes some wrong pre/post-indexed LDP and STP instructions, such as {ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE}, because when the offset type is C_UAUTO4K, pre and post don't work. Change-Id: Ifd901d4440eb06eb9e86c9dd17518749fdf32848 Reviewed-on: https://go-review.googlesource.com/c/go/+/273668 Trust: eric fang <eric.fang@arm.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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