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authoreric fang <eric.fang@arm.com>2021-06-21 02:11:25 +0000
committereric fang <eric.fang@arm.com>2021-06-29 02:34:20 +0000
commite2e05af6e189131162b533184eb04de5d597d544 (patch)
treec18cde83a3b17526fa77e0d13e521e365c134cb7 /src/cmd/asm
parent4bb0847b088eb3eb6122a18a87e1ca7756281dcc (diff)
downloadgo-e2e05af6e189131162b533184eb04de5d597d544.tar.gz
go-e2e05af6e189131162b533184eb04de5d597d544.zip
cmd/internal/obj/arm64: fix an encoding error of CMPW instruction
For arm64 CMP, ADD and other similar extended register instructions, if there is no extension, the default extion is LSL<<0, but the default encoding value (the value of 'option' field) of 32-bit instruction and 64-bit instruction is different, 32-bit is 2 and 64-bit is 3. But the current assembler incorrectly encodes the value of 32-bit instruction to 3. This CL fixes this error. Change-Id: I0e09af2c9c5047a4ed2db7d1183290283db9c31c Reviewed-on: https://go-review.googlesource.com/c/go/+/329749 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Trust: Dmitri Shuralyov <dmitshur@golang.org>
Diffstat (limited to 'src/cmd/asm')
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64.s3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 5f1e68545b..d8a20edfc1 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -89,7 +89,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
CMP R1<<33, R2
CMP R22.SXTX, RSP // ffe336eb
CMP $0x22220000, RSP // CMP $572653568, RSP // 5b44a4d2ff633beb
- CMPW $0x22220000, RSP // CMPW $572653568, RSP // 5b44a452ff633b6b
+ CMPW $0x22220000, RSP // CMPW $572653568, RSP // 5b44a452ff433b6b
CCMN MI, ZR, R1, $4 // e44341ba
// MADD Rn,Rm,Ra,Rd
MADD R1, R2, R3, R4 // 6408019b
@@ -377,6 +377,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
MOVD $0x1000100010001000, RSP // MOVD $1152939097061330944, RSP // ff8304b2
MOVW $0x10001000, RSP // MOVW $268439552, RSP // ff830432
ADDW $0x10001000, R1 // ADDW $268439552, R1 // fb83043221001b0b
+ ADDW $0x22220000, RSP, R3 // ADDW $572653568, RSP, R3 // 5b44a452e3433b0b
// move a large constant to a Vd.
VMOVS $0x80402010, V11 // VMOVS $2151686160, V11