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| author | Paul E. Murphy <murp@ibm.com> | 2021-04-16 15:15:17 -0500 |
|---|---|---|
| committer | Lynn Boger <laboger@linux.vnet.ibm.com> | 2021-04-22 17:02:01 +0000 |
| commit | d4aa72002e76c09f81a8fd82f37781f5126c9cbe (patch) | |
| tree | 28c56d149b7fdab45a3b63ca17e78932aad0c35c /src/cmd/asm | |
| parent | e8666abd9884f6743f78229ed210bf12a35e7368 (diff) | |
| download | go-d4aa72002e76c09f81a8fd82f37781f5126c9cbe.tar.gz go-d4aa72002e76c09f81a8fd82f37781f5126c9cbe.zip | |
cmd/asm: fix RLDCR const1,reg,const2,reg on ppc64
The extended opcode field (XO) is generated incorrectly. OPVCC
assumes an X-form like layout for the XO field. MD-form insns
also have an XO field, but it is both smaller and in a different
bit position.
This hasn't been noticed since const1 == 0 matches as a register
argument instead of a constant, thus it is unlikely anyone has
attempted to assemble this instruction with a non-zero shift
argument.
Likewise, update all other MD-form instructions using OPVCC
to use the new OPMD function.
Change-Id: Id81fa2727fb701431911a05492c2038415ad0a4d
Reviewed-on: https://go-review.googlesource.com/c/go/+/310851
Run-TryBot: Paul Murphy <murp@ibm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Trust: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/ppc64.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s index eaec24b8b7..edaecaea49 100644 --- a/src/cmd/asm/internal/asm/testdata/ppc64.s +++ b/src/cmd/asm/internal/asm/testdata/ppc64.s @@ -318,6 +318,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 RLDICCC $0, R4, $15, R6 // 788603c9 CLRLSLWI $16, R5, $8, R4 // 54a4422e CLRLSLDI $24, R4, $2, R3 // 78831588 + RLDCR $1, R1, $-16, R1 // 78210ee4 + RLDCRCC $1, R1, $-16, R1 // 78210ee5 BEQ 0(PC) // 41820000 BEQ CR1,0(PC) // 41860000 |