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path: root/src/cmd/internal/obj/riscv/obj.go
AgeCommit message (Expand)Author
2020-08-31cmd/compile,cmd/asm: simplify recording of branch targets, take 2Keith Randall
2020-08-28Revert "cmd/compile,cmd/asm: simplify recording of branch targets"Keith Randall
2020-08-27cmd/compile,cmd/asm: simplify recording of branch targetsKeith Randall
2020-05-06cmd/internal/obj, runtime: preempt & restart some instruction sequencesCherry Zhang
2020-04-16runtime: add async preemption support on riscv64Quey-Liang Kao
2020-03-31cmd/asm,cmd/internal/obj/riscv: provide branch pseudo-instructionsJoel Sing
2020-03-15cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructionsJoel Sing
2020-03-15cmd/internal/obj/riscv: add NOT pseudo-instructionJoel Sing
2020-03-15cmd/internal/obj/riscv: add FCLASSS/FCLASSD instructionsJoel Sing
2020-03-15cmd/asm,cmd/internal/obj/riscv: add atomic memory operation instructionsJoel Sing
2020-03-15cmd/asm,cmd/internal/obj/riscv: add LR/SC instructionsJoel Sing
2020-03-15cmd/internal/obj/riscv: add FENCE instructionJoel Sing
2020-03-15cmd/internal/obj/riscv: rework instruction generationJoel Sing
2020-03-15cmd/internal/obj/riscv: store relocation details in obj.Prog.RestArgsJoel Sing
2020-03-13cmd/asm, cmd/compile, runtime: add -spectre=ret modeRuss Cox
2020-01-29cmd/internal/obj/riscv,cmd/link: shorten the riscv64 call sequenceJoel Sing
2020-01-28cmd/internal/obj/riscv: use signed immediates for U-instructionsJoel Sing
2020-01-23cmd/internal/obj/riscv: restore the ADDI instruction in jalrToSymJoel Sing
2020-01-23cmd/internal/obj/riscv: add missing instructions to the ternary expansion listJoel Sing
2020-01-22cmd/internal/obj/riscv: implement prologue and epilogueJoel Sing
2020-01-21cmd/internal/obj/riscv: populate DWARF register mapping for riscv64Joel Sing
2020-01-21cmd/internal/obj/riscv: correctly split immediates for FLW/FLD/FSW/FSDJoel Sing
2020-01-18cmd/compile: implement compiler for riscv64Joel Sing
2020-01-04cmd/internal/obj/riscv: correct CALL reloc symbol handlingJoel Sing
2020-01-04cmd/internal/obj/riscv: handle MOV rewrites in separate passJoel Sing
2019-12-24cmd/internal/obj/riscv: handle AGETCALLERPCJoel Sing
2019-12-24cmd/internal/obj/riscv: handle FEQ/FNEG/SEQZ/SNEZJoel Sing
2019-12-24cmd/internal/obj/riscv: handle call, jmp and branchJoel Sing
2019-11-19cmd/internal/obj/riscv: split immediates larger than 12-bitsJoel Sing
2019-11-19cmd/link,cmd/internal/obj/riscv: implement archreloc for riscv64Joel Sing
2019-10-15cmd/internal/obj/riscv: implement MOV pseudo-instructionsJoel Sing
2019-09-26cmd/internal/obj/riscv: require memory targets for load and store instructionsJoel Sing
2019-09-26cmd/internal/obj/riscv: implement control transfer instructionsJoel Sing
2019-09-26cmd/internal/obj/riscv: implement AUIPC and LUI instructionsJoel Sing
2019-09-25cmd/internal/obj/riscv: implement floating point instructionsJoel Sing
2019-09-24cmd/internal/obj/riscv: implement RV64I integer computational instructionsJoel Sing
2019-09-24cmd/internal/obj/riscv: add environment call/breakpoint and base counter/time...Joel Sing
2019-09-20cmd/internal/obj/riscv: add load, store and multiplication instructionsJoel Sing
2019-09-17cmd/asm,cmd/internal/obj/riscv: implement integer computational instructionsJoel Sing
2019-09-12cmd/asm,cmd/internal/obj: initial support for riscv64 assemblerJoel Sing
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