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| author | Rob Pike <r@golang.org> | 2015-02-13 14:21:18 -0800 |
|---|---|---|
| committer | Rob Pike <r@golang.org> | 2015-02-13 23:08:51 +0000 |
| commit | 69ddb7a40849f9330170144dc82a1da9627acaa9 (patch) | |
| tree | e3e1950619dcc845d114d5edbe81cdceb62b7110 /src/runtime/memclr_arm.s | |
| parent | 2ecefd41fa853e40346e0f89c632efb8682c431b (diff) | |
| download | go-69ddb7a40849f9330170144dc82a1da9627acaa9.tar.gz go-69ddb7a40849f9330170144dc82a1da9627acaa9.zip | |
[dev.cc] all: edit assembly source for ARM to be more regular
Several .s files for ARM had several properties the new assembler will not support.
These include:
- mentioning SP or PC as a hardware register
These are always pseudo-registers except that in some contexts
they're not, and it's confusing because the context should not affect
which register you mean. Change the references to the hardware
registers to be explicit: R13 for SP, R15 for PC.
- constant creation using assignment
The files say a=b when they could instead say #define a b.
There is no reason to have both mechanisms.
- R(0) to refer to R0.
Some macros use this to a great extent. Again, it's easy just to
use a #define to rename a register.
Change-Id: I002335ace8e876c5b63c71c2560533eb835346d2
Reviewed-on: https://go-review.googlesource.com/4822
Reviewed-by: Dave Cheney <dave@cheney.net>
Diffstat (limited to 'src/runtime/memclr_arm.s')
| -rw-r--r-- | src/runtime/memclr_arm.s | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/runtime/memclr_arm.s b/src/runtime/memclr_arm.s index 1824d33b14..8b5fe31c51 100644 --- a/src/runtime/memclr_arm.s +++ b/src/runtime/memclr_arm.s @@ -25,31 +25,31 @@ #include "textflag.h" -TO = 8 -TOE = 11 -N = 12 -TMP = 12 /* N and TMP don't overlap */ +#define TO R8 +#define TOE R11 +#define N R12 +#define TMP R12 /* N and TMP don't overlap */ TEXT runtime·memclr(SB),NOSPLIT,$0-8 - MOVW ptr+0(FP), R(TO) - MOVW n+4(FP), R(N) - MOVW $0, R(0) + MOVW ptr+0(FP), TO + MOVW n+4(FP), N + MOVW $0, R0 - ADD R(N), R(TO), R(TOE) /* to end pointer */ + ADD N, TO, TOE /* to end pointer */ - CMP $4, R(N) /* need at least 4 bytes to copy */ + CMP $4, N /* need at least 4 bytes to copy */ BLT _1tail _4align: /* align on 4 */ - AND.S $3, R(TO), R(TMP) + AND.S $3, TO, TMP BEQ _4aligned - MOVBU.P R(0), 1(R(TO)) /* implicit write back */ + MOVBU.P R0, 1(TO) /* implicit write back */ B _4align _4aligned: - SUB $31, R(TOE), R(TMP) /* do 32-byte chunks if possible */ - CMP R(TMP), R(TO) + SUB $31, TOE, TMP /* do 32-byte chunks if possible */ + CMP TMP, TO BHS _4tail MOVW R0, R1 /* replicate */ @@ -61,26 +61,26 @@ _4aligned: MOVW R0, R7 _f32loop: - CMP R(TMP), R(TO) + CMP TMP, TO BHS _4tail - MOVM.IA.W [R0-R7], (R(TO)) + MOVM.IA.W [R0-R7], (TO) B _f32loop _4tail: - SUB $3, R(TOE), R(TMP) /* do remaining words if possible */ + SUB $3, TOE, TMP /* do remaining words if possible */ _4loop: - CMP R(TMP), R(TO) + CMP TMP, TO BHS _1tail - MOVW.P R(0), 4(R(TO)) /* implicit write back */ + MOVW.P R0, 4(TO) /* implicit write back */ B _4loop _1tail: - CMP R(TO), R(TOE) + CMP TO, TOE BEQ _return - MOVBU.P R(0), 1(R(TO)) /* implicit write back */ + MOVBU.P R0, 1(TO) /* implicit write back */ B _1tail _return: |