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| author | Joel Sing <joel@sing.id.au> | 2024-02-08 13:54:10 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2024-03-07 14:57:07 +0000 |
| commit | 997636760e2d981bb2f5ba486e0702e60a07ba16 (patch) | |
| tree | f4272eb6f8f4bd67d8b8c73e857f09233419a412 /src/crypto | |
| parent | 58052fe8e707cc0285cffb239bc7a5343243e316 (diff) | |
| download | go-997636760e2d981bb2f5ba486e0702e60a07ba16.tar.gz go-997636760e2d981bb2f5ba486e0702e60a07ba16.zip | |
cmd/compile,cmd/internal/obj: provide rotation pseudo-instructions for riscv64
Provide and use rotation pseudo-instructions for riscv64. The RISC-V bitmanip
extension adds support for hardware rotation instructions in the form of ROL,
ROLW, ROR, RORI, RORIW and RORW. These are easily implemented in the assembler
as pseudo-instructions for CPUs that do not support the bitmanip extension.
This approach provides a number of advantages, including reducing the rewrite
rules needed in the compiler, simplifying codegen tests and most importantly,
allowing these instructions to be used in assembly (for example, riscv64
optimised versions of SHA-256 and SHA-512). When bitmanip support is added,
these instruction sequences can simply be replaced with a single instruction
if permitted by the GORISCV64 profile.
Change-Id: Ia23402e1a82f211ac760690deb063386056ae1fa
Reviewed-on: https://go-review.googlesource.com/c/go/+/565015
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: M Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Diffstat (limited to 'src/crypto')
| -rw-r--r-- | src/crypto/sha512/sha512block_riscv64.s | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/src/crypto/sha512/sha512block_riscv64.s b/src/crypto/sha512/sha512block_riscv64.s index 6fbd524a31..7dcb0f80d0 100644 --- a/src/crypto/sha512/sha512block_riscv64.s +++ b/src/crypto/sha512/sha512block_riscv64.s @@ -46,11 +46,6 @@ // H6 = g + H6 // H7 = h + H7 -#define ROR(s, r, d, t1, t2) \ - SLL $(64-s), r, t1; \ - SRL $(s), r, t2; \ - OR t1, t2, d - // Wt = Mt; for 0 <= t <= 15 #define MSGSCHEDULE0(index) \ MOVBU ((index*8)+0)(X29), X5; \ @@ -85,14 +80,14 @@ MOV (((index-15)&0xf)*8)(X19), X6; \ MOV (((index-7)&0xf)*8)(X19), X9; \ MOV (((index-16)&0xf)*8)(X19), X21; \ - ROR(19, X5, X7, X23, X24); \ - ROR(61, X5, X8, X23, X24); \ + ROR $19, X5, X7; \ + ROR $61, X5, X8; \ SRL $6, X5; \ XOR X7, X5; \ XOR X8, X5; \ ADD X9, X5; \ - ROR(1, X6, X7, X23, X24); \ - ROR(8, X6, X8, X23, X24); \ + ROR $1, X6, X7; \ + ROR $8, X6, X8; \ SRL $7, X6; \ XOR X7, X6; \ XOR X8, X6; \ @@ -108,11 +103,11 @@ #define SHA512T1(index, e, f, g, h) \ MOV (index*8)(X18), X8; \ ADD X5, h; \ - ROR(14, e, X6, X23, X24); \ + ROR $14, e, X6; \ ADD X8, h; \ - ROR(18, e, X7, X23, X24); \ + ROR $18, e, X7; \ XOR X7, X6; \ - ROR(41, e, X8, X23, X24); \ + ROR $41, e, X8; \ XOR X8, X6; \ ADD X6, h; \ AND e, f, X5; \ @@ -126,10 +121,10 @@ // BIGSIGMA0(x) = ROTR(28,x) XOR ROTR(34,x) XOR ROTR(39,x) // Maj(x, y, z) = (x AND y) XOR (x AND z) XOR (y AND z) #define SHA512T2(a, b, c) \ - ROR(28, a, X6, X23, X24); \ - ROR(34, a, X7, X23, X24); \ + ROR $28, a, X6; \ + ROR $34, a, X7; \ XOR X7, X6; \ - ROR(39, a, X8, X23, X24); \ + ROR $39, a, X8; \ XOR X8, X6; \ AND a, b, X7; \ AND a, c, X8; \ |