diff options
| author | fanzha02 <fannie.zhang@arm.com> | 2020-08-20 17:02:18 +0800 |
|---|---|---|
| committer | fannie zhang <Fannie.Zhang@arm.com> | 2020-09-10 02:22:19 +0000 |
| commit | dfdc3880b01d46d1d8125ab9eea0606b2fa5b819 (patch) | |
| tree | 04c5845faacf93507fa0d24556d1dc80742e57bf /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | aa476ba6f43ebc4e7ddb6599a7ad35d9fbf1ec6d (diff) | |
| download | go-dfdc3880b01d46d1d8125ab9eea0606b2fa5b819.tar.gz go-dfdc3880b01d46d1d8125ab9eea0606b2fa5b819.zip | |
cmd/internal/obj/arm64: enable some SIMD instructions
Enable VBSL, VBIT, VCMTST, VUXTL VUXTL2 and FMOVQ SIMD
instructions required by the issue #40725. And FMOVQ
instrucion is used to move a large constant to a Vn
register.
Add test cases.
Fixes #40725
Change-Id: I1cac1922a0a0165d698a4b73a41f7a5f0a0ad549
Reviewed-on: https://go-review.googlesource.com/c/go/+/249758
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 9f377817a9..2a911b4cce 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -340,4 +340,9 @@ TEXT errors(SB),$0 MRS PMSWINC_EL0, R3 // ERROR "system register is not readable" MRS OSLAR_EL1, R3 // ERROR "system register is not readable" VLD3R.P 24(R15), [V15.H4,V16.H4,V17.H4] // ERROR "invalid post-increment offset" + VBIT V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VBSL V1.D2, V12.D2, V3.D2 // ERROR "invalid arrangement" + VUXTL V30.D2, V30.H8 // ERROR "operand mismatch" + VUXTL2 V20.B8, V21.H8 // ERROR "operand mismatch" + VUXTL V3.D2, V4.B8 // ERROR "operand mismatch" RET |