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| author | eric fang <eric.fang@arm.com> | 2021-06-21 03:04:42 +0000 |
|---|---|---|
| committer | eric fang <eric.fang@arm.com> | 2021-08-18 02:06:51 +0000 |
| commit | aef24d8f7db4fb895055e4543af958d7dc2eb8cc (patch) | |
| tree | 65936e5b435a144024f456d5e42c59e2940f2e66 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | ddfcc02352feb9e15ff9aa423bb49bfb37d689a3 (diff) | |
| download | go-aef24d8f7db4fb895055e4543af958d7dc2eb8cc.tar.gz go-aef24d8f7db4fb895055e4543af958d7dc2eb8cc.zip | |
cmd/internal/obj/arm64: fix the encoding error when operating with ZR
Some arm64 instructions accept ZR as its destination register, such as MOVD,
AND, ADD etc. although it doesn't seem to make much sense, but we should
make sure the encoding is correct. However there exists some encoding mistakes
in the current assembler, they are:
1, 'MOVD $1, ZR' is incorrectly encoded as 'MOVD $1, ZR' + '0x00000000'.
2, 'AND $1, R2, ZR' is incorrectly encoded as 'MOVD $1, R27' + 'AND R27, R2, ZR' +
'0x00000000'.
3, 'AND $1, ZR' is incorrectly encoded as 'AND $1, ZR, RSP'.
Obviously the first two encoding errors can cause SIGILL, and the third one will
rewrite RSP.
At the same time, I found some weird encodings but they don't cause errors.
4, 'MOVD $0x0001000100010001, ZR' is encoded as 'MOVW $1, ZR' + 'MOVKW $(1<<16), ZR'.
5, 'AND $0x0001000100010001, R2, ZR' is encoded as 'MOVD $1, R27' + 'MOVK $(1<<16), R27' +
'MOVK $(1<<32), R27'.
Some of these issues also apply to 32-bit versions of these instructions.
These problems are not very complicated, and are basically caused by the improper
adaptation of the class of the constant to the entry in the optab. But the relationship
between these constant classes is a bit complicated, so I don't know how to deal with
issue 4 and 5, because they won't cause errors, so this CL didn't deal with them.
This CL fixed the first three issues.
Issue 1:
before: 'MOVD $1, ZR' => 'MOVD $1, ZR' + '0x00000000'.
after: 'MOVD $1, ZR' => 'MOVD $1, ZR'.
Issue 2:
before: 'AND $1, R2, ZR' => 'MOVD $1, R27' + 'AND R27, R2, ZR' + '0x00000000'.
after: 'AND $1, R2, ZR' => 'ORR $1, ZR, R27' + 'AND R27, R2, ZR'.
Issue 3:
before: 'AND $1, ZR' => 'AND $1, ZR, RSP'.
after: 'AND $1, ZR' => 'ORR $1, ZR, R27' + 'AND R27, ZR, ZR'.
Change-Id: I3c889079229f847b863ad56c88966be12d947202
Reviewed-on: https://go-review.googlesource.com/c/go/+/329750
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Trust: eric fang <eric.fang@arm.com>
Run-TryBot: eric fang <eric.fang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index cf57179e43..145074347f 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -3,7 +3,7 @@ // license that can be found in the LICENSE file. TEXT errors(SB),$0 - AND $1, RSP // ERROR "illegal combination" + AND $1, RSP // ERROR "illegal source register" ANDS $1, R0, RSP // ERROR "illegal combination" ADDSW R7->32, R14, R13 // ERROR "shift amount out of range 0 to 31" ADD R1.UXTB<<5, R2, R3 // ERROR "shift amount out of range 0 to 4" |