diff options
| author | eric fang <eric.fang@arm.com> | 2021-04-21 03:12:20 +0000 |
|---|---|---|
| committer | eric fang <eric.fang@arm.com> | 2021-04-28 01:19:40 +0000 |
| commit | 9726c78539f4945087c837201c1ec3545a318389 (patch) | |
| tree | 377e22c003d5b6e7d6ca6ffb6bc3458bb366ac09 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | f439a762533f3a75eb928b67d0415010aa8a81d7 (diff) | |
| download | go-9726c78539f4945087c837201c1ec3545a318389.tar.gz go-9726c78539f4945087c837201c1ec3545a318389.zip | |
cmd/asm: add check for register and shift/extension combination on arm64
The current code lacks a check on whether the register and shift/extension
combination is valid, for example the follow instructions also compiles.
ADD F1<<1, R1, R3
ADD V1<<1, R1, R3
MOVW (R9)(F8.SXTW<<2), R19
VST1 R4.D[1], (R0)
Actually only general registers can perform shift operations, and element
and arrangement extensions are only applicable to vector registers. This
CL adds a check for the register and shift/extension combination on arm64.
Change-Id: I93dd9343e92a66899cba8eaf4e0ac5430e94692b
Reviewed-on: https://go-review.googlesource.com/c/go/+/312571
Trust: eric fang <eric.fang@arm.com>
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Keith Randall <khr@golang.org>
Run-TryBot: eric fang <eric.fang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index feb03abacd..66fc910759 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -96,13 +96,13 @@ TEXT errors(SB),$0 VMOV V8.H[9], R3 // ERROR "register element index out of range 0 to 7" VMOV V8.S[4], R3 // ERROR "register element index out of range 0 to 3" VMOV V8.D[2], R3 // ERROR "register element index out of range 0 to 1" - VDUP V8.B[16], R3.B16 // ERROR "register element index out of range 0 to 15" - VDUP V8.B[17], R3.B8 // ERROR "register element index out of range 0 to 15" - VDUP V8.H[9], R3.H4 // ERROR "register element index out of range 0 to 7" - VDUP V8.H[9], R3.H8 // ERROR "register element index out of range 0 to 7" - VDUP V8.S[4], R3.S2 // ERROR "register element index out of range 0 to 3" - VDUP V8.S[4], R3.S4 // ERROR "register element index out of range 0 to 3" - VDUP V8.D[2], R3.D2 // ERROR "register element index out of range 0 to 1" + VDUP V8.B[16], V3.B16 // ERROR "register element index out of range 0 to 15" + VDUP V8.B[17], V3.B8 // ERROR "register element index out of range 0 to 15" + VDUP V8.H[9], V3.H4 // ERROR "register element index out of range 0 to 7" + VDUP V8.H[9], V3.H8 // ERROR "register element index out of range 0 to 7" + VDUP V8.S[4], V3.S2 // ERROR "register element index out of range 0 to 3" + VDUP V8.S[4], V3.S4 // ERROR "register element index out of range 0 to 3" + VDUP V8.D[2], V3.D2 // ERROR "register element index out of range 0 to 1" VFMLA V1.D2, V12.D2, V3.S2 // ERROR "operand mismatch" VFMLA V1.S2, V12.S2, V3.D2 // ERROR "operand mismatch" VFMLA V1.S4, V12.S2, V3.D2 // ERROR "operand mismatch" |