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| author | fanzha02 <fannie.zhang@arm.com> | 2018-03-08 10:33:14 +0000 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-03-19 23:45:50 +0000 |
| commit | 910c3a9dfc4ff8ea4c25d725783bce4887d790f2 (patch) | |
| tree | 19d0954999c23541b920cd0055575475051f3d46 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | 7974f0815e071448cd429d7c30c1d6c24b04a589 (diff) | |
| download | go-910c3a9dfc4ff8ea4c25d725783bce4887d790f2.tar.gz go-910c3a9dfc4ff8ea4c25d725783bce4887d790f2.zip | |
cmd/asm: add ARM64 assembler check for incorrect input
Current ARM64 assembler has no check for the invalid value of both
shift amount and post-index immediate offset of LD1/ST1. This patch
adds the check.
This patch also fixes the printing error of register number equals
to 31, which should be printed as ZR instead of R31. Test cases
are also added.
Change-Id: I476235f3ab3a3fc91fe89c5a3149a4d4529c05c7
Reviewed-on: https://go-review.googlesource.com/100255
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 105 |
1 files changed, 55 insertions, 50 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 93c3acdc3b..dcdb4fe175 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -3,54 +3,59 @@ // license that can be found in the LICENSE file. TEXT errors(SB),$0 - MOVD.P 300(R2), R3 // ERROR "offset out of range [-255,254]" - MOVD.P R3, 344(R2) // ERROR "offset out of range [-255,254]" - VLD1 (R8)(R13), [V2.B16] // ERROR "illegal combination" - VLD1 8(R9), [V2.B16] // ERROR "illegal combination" - VST1 [V1.B16], (R8)(R13) // ERROR "illegal combination" - VST1 [V1.B16], 9(R2) // ERROR "illegal combination" - VLD1 8(R8)(R13), [V2.B16] // ERROR "illegal combination" - ADD R1.UXTB<<5, R2, R3 // ERROR "shift amount out of range 0 to 4" - ADDS R1.UXTX<<7, R2, R3 // ERROR "shift amount out of range 0 to 4" - VMOV V8.D[2], V12.D[1] // ERROR "register element index out of range 0 to 1" - VMOV V8.S[4], V12.S[1] // ERROR "register element index out of range 0 to 3" - VMOV V8.H[8], V12.H[1] // ERROR "register element index out of range 0 to 7" - VMOV V8.B[16], V12.B[1] // ERROR "register element index out of range 0 to 15" - VMOV V8.D[0], V12.S[1] // ERROR "operand mismatch" - VMOV V8.D[0], V12.H[1] // ERROR "operand mismatch" - VMOV V8.D[0], V12.B[1] // ERROR "operand mismatch" - VMOV V8.S[0], V12.H[1] // ERROR "operand mismatch" - VMOV V8.S[0], V12.B[1] // ERROR "operand mismatch" - VMOV V8.H[0], V12.B[1] // ERROR "operand mismatch" - VMOV V8.B[16], R3 // ERROR "register element index out of range 0 to 15" - VMOV V8.H[9], R3 // ERROR "register element index out of range 0 to 7" - VMOV V8.S[4], R3 // ERROR "register element index out of range 0 to 3" - VMOV V8.D[2], R3 // ERROR "register element index out of range 0 to 1" - VDUP V8.B[16], R3.B16 // ERROR "register element index out of range 0 to 15" - VDUP V8.B[17], R3.B8 // ERROR "register element index out of range 0 to 15" - VDUP V8.H[9], R3.H4 // ERROR "register element index out of range 0 to 7" - VDUP V8.H[9], R3.H8 // ERROR "register element index out of range 0 to 7" - VDUP V8.S[4], R3.S2 // ERROR "register element index out of range 0 to 3" - VDUP V8.S[4], R3.S4 // ERROR "register element index out of range 0 to 3" - VDUP V8.D[2], R3.D2 // ERROR "register element index out of range 0 to 1" - VFMLA V1.D2, V12.D2, V3.S2 // ERROR "operand mismatch" - VFMLA V1.S2, V12.S2, V3.D2 // ERROR "operand mismatch" - VFMLA V1.S4, V12.S2, V3.D2 // ERROR "operand mismatch" - VFMLA V1.H4, V12.H4, V3.D2 // ERROR "operand mismatch" - VFMLS V1.S2, V12.S2, V3.S4 // ERROR "operand mismatch" - VFMLS V1.S2, V12.D2, V3.S4 // ERROR "operand mismatch" - VFMLS V1.S2, V12.S4, V3.D2 // ERROR "operand mismatch" - VFMLA V1.B8, V12.B8, V3.B8 // ERROR "invalid arrangement" - VFMLA V1.B16, V12.B16, V3.B16 // ERROR "invalid arrangement" - VFMLA V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" - VFMLA V1.H8, V12.H8, V3.H8 // ERROR "invalid arrangement" - VFMLA V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" - VFMLS V1.B8, V12.B8, V3.B8 // ERROR "invalid arrangement" - VFMLS V1.B16, V12.B16, V3.B16 // ERROR "invalid arrangement" - VFMLS V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" - VFMLS V1.H8, V12.H8, V3.H8 // ERROR "invalid arrangement" - VFMLS V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" - - AND $1, RSP // ERROR "illegal combination" - ANDS $1, R0, RSP // ERROR "illegal combination" + AND $1, RSP // ERROR "illegal combination" + ANDS $1, R0, RSP // ERROR "illegal combination" + MOVD.P 300(R2), R3 // ERROR "offset out of range [-255,254]" + MOVD.P R3, 344(R2) // ERROR "offset out of range [-255,254]" + ADDSW R7->32, R14, R13 // ERROR "shift amount out of range 0 to 31" + BICW R7@>33, R5, R16 // ERROR "shift amount out of range 0 to 31" + ADD R1.UXTB<<5, R2, R3 // ERROR "shift amount out of range 0 to 4" + ADDS R1.UXTX<<7, R2, R3 // ERROR "shift amount out of range 0 to 4" + VLD1 (R8)(R13), [V2.B16] // ERROR "illegal combination" + VLD1 8(R9), [V2.B16] // ERROR "illegal combination" + VST1 [V1.B16], (R8)(R13) // ERROR "illegal combination" + VST1 [V1.B16], 9(R2) // ERROR "illegal combination" + VLD1 8(R8)(R13), [V2.B16] // ERROR "illegal combination" + VMOV V8.D[2], V12.D[1] // ERROR "register element index out of range 0 to 1" + VMOV V8.S[4], V12.S[1] // ERROR "register element index out of range 0 to 3" + VMOV V8.H[8], V12.H[1] // ERROR "register element index out of range 0 to 7" + VMOV V8.B[16], V12.B[1] // ERROR "register element index out of range 0 to 15" + VMOV V8.D[0], V12.S[1] // ERROR "operand mismatch" + VMOV V8.D[0], V12.H[1] // ERROR "operand mismatch" + VMOV V8.D[0], V12.B[1] // ERROR "operand mismatch" + VMOV V8.S[0], V12.H[1] // ERROR "operand mismatch" + VMOV V8.S[0], V12.B[1] // ERROR "operand mismatch" + VMOV V8.H[0], V12.B[1] // ERROR "operand mismatch" + VMOV V8.B[16], R3 // ERROR "register element index out of range 0 to 15" + VMOV V8.H[9], R3 // ERROR "register element index out of range 0 to 7" + VMOV V8.S[4], R3 // ERROR "register element index out of range 0 to 3" + VMOV V8.D[2], R3 // ERROR "register element index out of range 0 to 1" + VDUP V8.B[16], R3.B16 // ERROR "register element index out of range 0 to 15" + VDUP V8.B[17], R3.B8 // ERROR "register element index out of range 0 to 15" + VDUP V8.H[9], R3.H4 // ERROR "register element index out of range 0 to 7" + VDUP V8.H[9], R3.H8 // ERROR "register element index out of range 0 to 7" + VDUP V8.S[4], R3.S2 // ERROR "register element index out of range 0 to 3" + VDUP V8.S[4], R3.S4 // ERROR "register element index out of range 0 to 3" + VDUP V8.D[2], R3.D2 // ERROR "register element index out of range 0 to 1" + VFMLA V1.D2, V12.D2, V3.S2 // ERROR "operand mismatch" + VFMLA V1.S2, V12.S2, V3.D2 // ERROR "operand mismatch" + VFMLA V1.S4, V12.S2, V3.D2 // ERROR "operand mismatch" + VFMLA V1.H4, V12.H4, V3.D2 // ERROR "operand mismatch" + VFMLS V1.S2, V12.S2, V3.S4 // ERROR "operand mismatch" + VFMLS V1.S2, V12.D2, V3.S4 // ERROR "operand mismatch" + VFMLS V1.S2, V12.S4, V3.D2 // ERROR "operand mismatch" + VFMLA V1.B8, V12.B8, V3.B8 // ERROR "invalid arrangement" + VFMLA V1.B16, V12.B16, V3.B16 // ERROR "invalid arrangement" + VFMLA V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VFMLA V1.H8, V12.H8, V3.H8 // ERROR "invalid arrangement" + VFMLA V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VFMLS V1.B8, V12.B8, V3.B8 // ERROR "invalid arrangement" + VFMLS V1.B16, V12.B16, V3.B16 // ERROR "invalid arrangement" + VFMLS V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VFMLS V1.H8, V12.H8, V3.H8 // ERROR "invalid arrangement" + VFMLS V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VST1.P [V4.S4,V5.S4], 48(R1) // ERROR "invalid post-increment offset" + VST1.P [V4.S4], 8(R1) // ERROR "invalid post-increment offset" + VLD1.P 32(R1), [V8.S4, V9.S4, V10.S4] // ERROR "invalid post-increment offset" + VLD1.P 48(R1), [V7.S4, V8.S4, V9.S4, V10.S4] // ERROR "invalid post-increment offset" RET |