diff options
| author | fanzha02 <fannie.zhang@arm.com> | 2018-06-15 10:20:00 +0000 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-09-06 19:42:03 +0000 |
| commit | 7ab4b5586d37513bfa48f769773007ff8e9b732d (patch) | |
| tree | 4a26ef2d8e08d5e85b5602c32e89513845794f6e /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | 9c2be4c22d78cebc52458ba7298a470a3be0cdce (diff) | |
| download | go-7ab4b5586d37513bfa48f769773007ff8e9b732d.tar.gz go-7ab4b5586d37513bfa48f769773007ff8e9b732d.zip | |
cmd/internal/obj/arm64: add CONSTRAINED UNPREDICTABLE behavior check for some load/store
According to ARM64 manual, it is "constrained unpredictable behavior"
if the src and dst registers of some load/store instructions are same.
In order to completely prevent such unpredictable behavior, adding the
check for load/store instructions that are supported by the assembler
in the assembler.
Add test cases.
Update #25823
Change-Id: I64c14ad99ee543d778e7ec8ae6516a532293dbb3
Reviewed-on: https://go-review.googlesource.com/120660
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index b2ec0cc425..bbdce479c5 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -8,7 +8,19 @@ TEXT errors(SB),$0 ADDSW R7->32, R14, R13 // ERROR "shift amount out of range 0 to 31" ADD R1.UXTB<<5, R2, R3 // ERROR "shift amount out of range 0 to 4" ADDS R1.UXTX<<7, R2, R3 // ERROR "shift amount out of range 0 to 4" + AND $0x22220000, R2, RSP // ERROR "illegal combination" + ANDS $0x22220000, R2, RSP // ERROR "illegal combination" + ADD R1, R2, R3, R4 // ERROR "illegal combination" BICW R7@>33, R5, R16 // ERROR "shift amount out of range 0 to 31" + CINC CS, R2, R3, R4 // ERROR "illegal combination" + CSEL LT, R1, R2 // ERROR "illegal combination" + LDP.P 8(R2), (R2, R3) // ERROR "constrained unpredictable behavior" + LDP.W 8(R3), (R2, R3) // ERROR "constrained unpredictable behavior" + LDP (R1), (R2, R2) // ERROR "constrained unpredictable behavior" + LDP (R0), (F0, F1) // ERROR "invalid register pair" + LDP (R0), (R3, ZR) // ERROR "invalid register pair" + LDXPW (RSP), (R2, R2) // ERROR "constrained unpredictable behavior" + LDAXPW (R5), (R2, R2) // ERROR "constrained unpredictable behavior" MOVD.P 300(R2), R3 // ERROR "offset out of range [-255,254]" MOVD.P R3, 344(R2) // ERROR "offset out of range [-255,254]" MOVD (R3)(R7.SXTX<<2), R8 // ERROR "invalid index shift amount" @@ -16,6 +28,17 @@ TEXT errors(SB),$0 MOVWU (R5)(R4<<1), R10 // ERROR "invalid index shift amount" MOVB (R5)(R4.SXTW<<5), R10 // ERROR "invalid index shift amount" MOVH R5, (R6)(R2<<3) // ERROR "invalid index shift amount" + MADD R1, R2, R3 // ERROR "illegal combination" + MOVD.P R1, 8(R1) // ERROR "constrained unpredictable behavior" + MOVD.W 16(R2), R2 // ERROR "constrained unpredictable behavior" + STP (F2, F3), (R0) // ERROR "invalid register pair" + STP.W (R1, R2), 8(R1) // ERROR "constrained unpredictable behavior" + STP.P (R1, R2), 8(R2) // ERROR "constrained unpredictable behavior" + STLXP (R6, R11), (RSP), R6 // ERROR "constrained unpredictable behavior" + STXP (R6, R11), (R2), R2 // ERROR "constrained unpredictable behavior" + STLXR R3, (RSP), R3 // ERROR "constrained unpredictable behavior" + STXR R3, (R4), R4 // ERROR "constrained unpredictable behavior" + STLXRB R2, (R5), R5 // ERROR "constrained unpredictable behavior" VLD1 (R8)(R13), [V2.B16] // ERROR "illegal combination" VLD1 8(R9), [V2.B16] // ERROR "illegal combination" VST1 [V1.B16], (R8)(R13) // ERROR "illegal combination" @@ -83,15 +106,8 @@ TEXT errors(SB),$0 VST1.P [V1.B16], (R8)(R9<<1) // ERROR "invalid extended register" VREV64 V1.H4, V2.H8 // ERROR "invalid arrangement" VREV64 V1.D1, V2.D1 // ERROR "invalid arrangement" - ADD R1, R2, R3, R4 // ERROR "illegal combination" - MADD R1, R2, R3 // ERROR "illegal combination" - CINC CS, R2, R3, R4 // ERROR "illegal combination" - CSEL LT, R1, R2 // ERROR "illegal combination" - AND $0x22220000, R2, RSP // ERROR "illegal combination" - ANDS $0x22220000, R2, RSP // ERROR "illegal combination" - LDP (R0), (F0, F1) // ERROR "invalid register pair" - LDP (R0), (R3, ZR) // ERROR "invalid register pair" - STP (F2, F3), (R0) // ERROR "invalid register pair" FLDPD (R0), (R1, R2) // ERROR "invalid register pair" + FLDPD (R1), (F2, F2) // ERROR "constrained unpredictable behavior" + FLDPS (R2), (F3, F3) // ERROR "constrained unpredictable behavior" FSTPD (R1, R2), (R0) // ERROR "invalid register pair" RET |