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| author | eric fang <eric.fang@arm.com> | 2021-04-13 02:48:32 +0000 |
|---|---|---|
| committer | eric fang <eric.fang@arm.com> | 2021-04-15 01:54:41 +0000 |
| commit | 48b7432e3f5318a026842fc4f39fb690e13f79f8 (patch) | |
| tree | f88afa9b60c7568f7ed83b6af0ed79fe193a7d84 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | 566a87c16b055872cb469d46cbccc2404dba9bb7 (diff) | |
| download | go-48b7432e3f5318a026842fc4f39fb690e13f79f8.tar.gz go-48b7432e3f5318a026842fc4f39fb690e13f79f8.zip | |
cmd/internal/obj/arm64: fix the wrong sp dst register of ADDS/SUBS instructions
According the armv8-a specification, the destination register of the ADDS/ADDSW/
SUBS/SUBSW instructions can not be RSP, the current implementation does not
check this and encodes this wrong instruction format as a CMN instruction. This
CL adds a check and test cases for this situation.
Change-Id: I92cc2f8e17dbda70f0dce8fddf1ca6d5d7730589
Reviewed-on: https://go-review.googlesource.com/c/go/+/309989
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Trust: eric fang <eric.fang@arm.com>
Run-TryBot: eric fang <eric.fang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 64bade2051..474ed556d0 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -8,6 +8,26 @@ TEXT errors(SB),$0 ADDSW R7->32, R14, R13 // ERROR "shift amount out of range 0 to 31" ADD R1.UXTB<<5, R2, R3 // ERROR "shift amount out of range 0 to 4" ADDS R1.UXTX<<7, R2, R3 // ERROR "shift amount out of range 0 to 4" + ADDS R5, R6, RSP // ERROR "illegal destination register" + SUBS R5, R6, RSP // ERROR "illegal destination register" + ADDSW R5, R6, RSP // ERROR "illegal destination register" + SUBSW R5, R6, RSP // ERROR "illegal destination register" + ADDS $0xff, R6, RSP // ERROR "illegal destination register" + ADDS $0xffff0, R6, RSP // ERROR "illegal destination register" + ADDS $0x1000100010001000, R6, RSP // ERROR "illegal destination register" + ADDS $0x10001000100011, R6, RSP // ERROR "illegal destination register" + ADDSW $0xff, R6, RSP // ERROR "illegal destination register" + ADDSW $0xffff0, R6, RSP // ERROR "illegal destination register" + ADDSW $0x1000100010001000, R6, RSP // ERROR "illegal destination register" + ADDSW $0x10001000100011, R6, RSP // ERROR "illegal destination register" + SUBS $0xff, R6, RSP // ERROR "illegal destination register" + SUBS $0xffff0, R6, RSP // ERROR "illegal destination register" + SUBS $0x1000100010001000, R6, RSP // ERROR "illegal destination register" + SUBS $0x10001000100011, R6, RSP // ERROR "illegal destination register" + SUBSW $0xff, R6, RSP // ERROR "illegal destination register" + SUBSW $0xffff0, R6, RSP // ERROR "illegal destination register" + SUBSW $0x1000100010001000, R6, RSP // ERROR "illegal destination register" + SUBSW $0x10001000100011, R6, RSP // ERROR "illegal destination register" AND $0x22220000, R2, RSP // ERROR "illegal combination" ANDS $0x22220000, R2, RSP // ERROR "illegal combination" ADD R1, R2, R3, R4 // ERROR "illegal combination" |