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| author | eric fang <eric.fang@arm.com> | 2021-04-20 02:46:33 +0000 |
|---|---|---|
| committer | Eric Fang <eric.fang@arm.com> | 2022-03-15 01:00:36 +0000 |
| commit | 44a0da4ff11a5447dcfe2b62ac46bca134736d81 (patch) | |
| tree | 6cbcfa8a4abcffdb943d61f16da9597cd93dab26 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | 41a82aa9c36bffab2593d50aa55a462fef4e5bd4 (diff) | |
| download | go-44a0da4ff11a5447dcfe2b62ac46bca134736d81.tar.gz go-44a0da4ff11a5447dcfe2b62ac46bca134736d81.zip | |
cmd/internal/obj/arm64: refactor the handling of shifted RSP
Some arithmetic operation instructions such as ADD and SUB support two
formats of left shift (<<) operation, namely shifted register format and
extended register format. And the encoding, supported registers and shifted
amount are both different.
The assembly parser doesn't distinguish them and parses them into TYPE_SHIFT
type, because the parser can't tell them apart and in most cases extended
left-shift can be replaced by shifted left-shift. The only exception is
when the second source register or the destination register is RSP.
This CL converts this case into the extended format in the preprocess stage,
which helps to simplify some of the logic of the new assembler implementation
and also makes this situation look more reasonable.
Change-Id: I2cd7d2d663b38a7ba77a9fef1092708b8cb9bc3d
Reviewed-on: https://go-review.googlesource.com/c/go/+/311709
Trust: Eric Fang <eric.fang@arm.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 3d3de1d9b1..033c4cda6c 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -417,8 +417,8 @@ TEXT errors(SB),$0 CASPD (R2, R4), (R2), (R8, R9) // ERROR "source register pair must be contiguous" CASPD (R2, R3), (R2), (R8, R10) // ERROR "destination register pair must be contiguous" ADD R1>>2, RSP, R3 // ERROR "illegal combination" - ADDS R2<<3, R3, RSP // ERROR "unexpected SP reference" - CMP R1<<5, RSP // ERROR "the left shift amount out of range 0 to 4" + ADDS R2<<3, R3, RSP // ERROR "illegal destination register" + CMP R1<<5, RSP // ERROR "shift amount out of range 0 to 4" MOVD.P y+8(FP), R1 // ERROR "illegal combination" MOVD.W x-8(SP), R1 // ERROR "illegal combination" LDP.P x+8(FP), (R0, R1) // ERROR "illegal combination" |