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author | erifan01 <eric.fang@arm.com> | 2020-08-12 17:41:54 +0800 |
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committer | Eric Fang <eric.fang@arm.com> | 2022-04-01 06:36:16 +0000 |
commit | 26ab2159694b19ef5feb56f4fe7a9cd18360dcdd (patch) | |
tree | 616bff0a2fe2990a3c856fc31546c71a8aafd647 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
parent | 029d2c4524e729dbd913475ca4a5138bb6c5e099 (diff) | |
download | go-26ab2159694b19ef5feb56f4fe7a9cd18360dcdd.tar.gz go-26ab2159694b19ef5feb56f4fe7a9cd18360dcdd.zip |
cmd/asm: add TLBI instruction on arm64
There was only a placeholder for TLBI instruction in the previous code.
gVisor needs this instruction. This CL completes its support.
This patch is a copy of CL 250758, contributed by Junchen Li(junchen.li@arm.com).
Co-authored-by: Junchen Li(junchen.li@arm.com)
Change-Id: I69e893d2c1f75e227475de9e677548e14870f3cd
Reviewed-on: https://go-review.googlesource.com/c/go/+/302850
Reviewed-by: Cherry Mui <cherryyz@google.com>
Trust: Eric Fang <eric.fang@arm.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
-rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 033c4cda6c..a41f180bb6 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -432,4 +432,9 @@ TEXT errors(SB),$0 STP (R26, R27), 700(R2) // ERROR "cannot use REGTMP as source" MOVK $0, R10 // ERROR "zero shifts cannot be handled correctly" MOVK $(0<<32), R10 // ERROR "zero shifts cannot be handled correctly" + TLBI PLDL1KEEP // ERROR "illegal argument" + TLBI VMALLE1IS, R0 // ERROR "extraneous register at operand 2" + TLBI ALLE3OS, ZR // ERROR "extraneous register at operand 2" + TLBI VAE1IS // ERROR "missing register at operand 2" + TLBI RVALE3 // ERROR "missing register at operand 2" RET |