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| author | Rob Findley <rfindley@google.com> | 2020-09-11 14:23:34 -0400 |
|---|---|---|
| committer | Rob Findley <rfindley@google.com> | 2020-09-11 14:23:34 -0400 |
| commit | f8b1c17aced24a1618c6984794be9770c5d260be (patch) | |
| tree | 45af8d39b5c3d9f43d439ebec0a2ba42b49efe70 /src/cmd/asm/internal/asm/testdata/arm64error.s | |
| parent | e5d91ab096a9ff9673311f1a7f3f860a7f9c2062 (diff) | |
| parent | 07c1788357cfe6a4ee5f6f6a54d4fe9f579fa844 (diff) | |
| download | go-dev.types.tar.gz go-dev.types.zip | |
[dev.types] all: merge master into dev.typesdev.types
Change-Id: Ia6964cb4e09153c15cc9c5b441373d1b3cb8f757
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/arm64error.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 0661a474b4..20b1f3e9f0 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -339,4 +339,18 @@ TEXT errors(SB),$0 MRS ICV_EOIR1_EL1, R3 // ERROR "system register is not readable" MRS PMSWINC_EL0, R3 // ERROR "system register is not readable" MRS OSLAR_EL1, R3 // ERROR "system register is not readable" + VLD3R.P 24(R15), [V15.H4,V16.H4,V17.H4] // ERROR "invalid post-increment offset" + VBIT V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" + VBSL V1.D2, V12.D2, V3.D2 // ERROR "invalid arrangement" + VUXTL V30.D2, V30.H8 // ERROR "operand mismatch" + VUXTL2 V20.B8, V21.H8 // ERROR "operand mismatch" + VUXTL V3.D2, V4.B8 // ERROR "operand mismatch" + VUZP1 V0.B8, V30.B8, V1.B16 // ERROR "operand mismatch" + VUZP2 V0.Q1, V30.Q1, V1.Q1 // ERROR "invalid arrangement" + VUSHLL $0, V30.D2, V30.H8 // ERROR "operand mismatch" + VUSHLL2 $0, V20.B8, V21.H8 // ERROR "operand mismatch" + VUSHLL $8, V30.B8, V30.H8 // ERROR "shift amount out of range" + VUSHLL2 $32, V30.S4, V2.D2 // ERROR "shift amount out of range" + VBIF V0.B8, V1.B8, V2.B16 // ERROR "operand mismatch" + VBIF V0.D2, V1.D2, V2.D2 // ERROR "invalid arrangement" RET |