cmd/asm: add DC instruction on arm64

There was only a placeholder for DC instruction in the previous code.
gVisor needs this instruction. This CL completes its support.

This patch is a copy of CL 250858, contributed by Junchen Li(junchen.li@arm.com).
Co-authored-by: Junchen Li(junchen.li@arm.com)

CustomizedGitHooks: yes
Change-Id: I76098048a227fbd08aa42c4173b028f0ab4f66e8
Reviewed-on: https://go-review.googlesource.com/c/go/+/302851
Reviewed-by: Cherry Mui <cherryyz@google.com>
Trust: Eric Fang <eric.fang@arm.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>

6 files changed, 147 insertions, 26 deletions

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 7866cf1db0..0e5799a022 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -1710,4 +1710,34 @@ again:
 	TLBI	RVALE3OS, ZR                       // bf850ed5
 	TLBI	RVAE3, R29                         // 3d860ed5
 	TLBI	RVALE3, R30                        // be860ed5
+
+// DC instruction
+	DC	IVAC, R0                           // 207608d5
+	DC	ISW, R1                            // 417608d5
+	DC	CSW, R2                            // 427a08d5
+	DC	CISW, R3                           // 437e08d5
+	DC	ZVA, R4                            // 24740bd5
+	DC	CVAC, R5                           // 257a0bd5
+	DC	CVAU, R6                           // 267b0bd5
+	DC	CIVAC, R7                          // 277e0bd5
+	DC	IGVAC, R8                          // 687608d5
+	DC	IGSW, R9                           // 897608d5
+	DC	IGDVAC, R10                        // aa7608d5
+	DC	IGDSW, R11                         // cb7608d5
+	DC	CGSW, R12                          // 8c7a08d5
+	DC	CGDSW, R13                         // cd7a08d5
+	DC	CIGSW, R14                         // 8e7e08d5
+	DC	CIGDSW, R15                        // cf7e08d5
+	DC	GVA, R16                           // 70740bd5
+	DC	GZVA, R17                          // 91740bd5
+	DC	CGVAC, ZR                          // 7f7a0bd5
+	DC	CGDVAC, R19                        // b37a0bd5
+	DC	CGVAP, R20                         // 747c0bd5
+	DC	CGDVAP, R21                        // b57c0bd5
+	DC	CGVADP, R22                        // 767d0bd5
+	DC	CGDVADP, R23                       // b77d0bd5
+	DC	CIGVAC, R24                        // 787e0bd5
+	DC	CIGDVAC, R25                       // b97e0bd5
+	DC	CVAP, R26                          // 3a7c0bd5
+	DC	CVADP, R27                         // 3b7d0bd5
 	END
diff --git a/src/cmd/asm/internal/asm/testdata/arm64enc.s b/src/cmd/asm/internal/asm/testdata/arm64enc.s
index f08e953c98..eff48ae8e7 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64enc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64enc.s
@@ -134,7 +134,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
    CSINV LO, R2, R11, R14                     // 4e308bda
    CSNEGW HS, R16, R29, R10                   // 0a269d5a
    CSNEG NE, R21, R19, R11                    // ab1693da
-   //TODO DC
+   DC IVAC, R1                                // 217608d5
    DCPS1 $11378                               // 418ea5d4
    DCPS2 $10699                               // 6239a5d4
    DCPS3 $24415                               // e3ebabd4
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index a41f180bb6..52f01e16a6 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -437,4 +437,9 @@ TEXT errors(SB),$0
 	TLBI	ALLE3OS, ZR                                      // ERROR "extraneous register at operand 2"
 	TLBI	VAE1IS                                           // ERROR "missing register at operand 2"
 	TLBI	RVALE3                                           // ERROR "missing register at operand 2"
+	DC	PLDL1KEEP                                        // ERROR "illegal argument"
+	DC	VMALLE1IS                                        // ERROR "illegal argument"
+	DC	VAE1IS                                           // ERROR "illegal argument"
+	DC	VAE1IS, R0                                       // ERROR "illegal argument"
+	DC	IVAC                                             // ERROR "missing register at operand 2"
 	RET
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index c34b00db70..d6522f5738 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -1154,6 +1154,36 @@ const (
 	SPOP_RVAE3
 	SPOP_RVALE3
 
+	// DC
+	SPOP_IVAC
+	SPOP_ISW
+	SPOP_CSW
+	SPOP_CISW
+	SPOP_ZVA
+	SPOP_CVAC
+	SPOP_CVAU
+	SPOP_CIVAC
+	SPOP_IGVAC
+	SPOP_IGSW
+	SPOP_IGDVAC
+	SPOP_IGDSW
+	SPOP_CGSW
+	SPOP_CGDSW
+	SPOP_CIGSW
+	SPOP_CIGDSW
+	SPOP_GVA
+	SPOP_GZVA
+	SPOP_CGVAC
+	SPOP_CGDVAC
+	SPOP_CGVAP
+	SPOP_CGDVAP
+	SPOP_CGVADP
+	SPOP_CGDVADP
+	SPOP_CIGVAC
+	SPOP_CIGDVAC
+	SPOP_CVAP
+	SPOP_CVADP
+
 	// PSTATE fields
 	SPOP_DAIFSet
 	SPOP_DAIFClr
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 7e1ae15513..72c4cd48ed 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -998,6 +998,35 @@ var sysInstFields = map[SpecialOperand]struct {
 	SPOP_RVALE3OS:     {6, 8, 5, 5, true},
 	SPOP_RVAE3:        {6, 8, 6, 1, true},
 	SPOP_RVALE3:       {6, 8, 6, 5, true},
+	// DC
+	SPOP_IVAC:    {0, 7, 6, 1, true},
+	SPOP_ISW:     {0, 7, 6, 2, true},
+	SPOP_CSW:     {0, 7, 10, 2, true},
+	SPOP_CISW:    {0, 7, 14, 2, true},
+	SPOP_ZVA:     {3, 7, 4, 1, true},
+	SPOP_CVAC:    {3, 7, 10, 1, true},
+	SPOP_CVAU:    {3, 7, 11, 1, true},
+	SPOP_CIVAC:   {3, 7, 14, 1, true},
+	SPOP_IGVAC:   {0, 7, 6, 3, true},
+	SPOP_IGSW:    {0, 7, 6, 4, true},
+	SPOP_IGDVAC:  {0, 7, 6, 5, true},
+	SPOP_IGDSW:   {0, 7, 6, 6, true},
+	SPOP_CGSW:    {0, 7, 10, 4, true},
+	SPOP_CGDSW:   {0, 7, 10, 6, true},
+	SPOP_CIGSW:   {0, 7, 14, 4, true},
+	SPOP_CIGDSW:  {0, 7, 14, 6, true},
+	SPOP_GVA:     {3, 7, 4, 3, true},
+	SPOP_GZVA:    {3, 7, 4, 4, true},
+	SPOP_CGVAC:   {3, 7, 10, 3, true},
+	SPOP_CGDVAC:  {3, 7, 10, 5, true},
+	SPOP_CGVAP:   {3, 7, 12, 3, true},
+	SPOP_CGDVAP:  {3, 7, 12, 5, true},
+	SPOP_CGVADP:  {3, 7, 13, 3, true},
+	SPOP_CGDVADP: {3, 7, 13, 5, true},
+	SPOP_CIGVAC:  {3, 7, 14, 3, true},
+	SPOP_CIGDVAC: {3, 7, 14, 5, true},
+	SPOP_CVAP:    {3, 7, 12, 1, true},
+	SPOP_CVADP:   {3, 7, 13, 1, true},
 }
 
 // Used for padinng NOOP instruction
@@ -2963,11 +2992,10 @@ func buildop(ctxt *obj.Link) {
 
 		case ASYS:
 			oprangeset(AAT, t)
-			oprangeset(ADC, t)
 			oprangeset(AIC, t)
 
 		case ATLBI:
-			break
+			oprangeset(ADC, t)
 
 		case ASYSL, AHINT:
 			break
@@ -5609,9 +5637,9 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
 		}
 		o1 |= enc | uint32(rs&31)<<16 | uint32(rb&31)<<5 | uint32(rt&31)
 
-	case 107: /* tlbi */
+	case 107: /* tlbi, dc */
 		op, ok := sysInstFields[SpecialOperand(p.From.Offset)]
-		if !ok || (p.As == ATLBI && op.cn != 8) {
+		if !ok || (p.As == ATLBI && op.cn != 8) || (p.As == ADC && op.cn != 7) {
 			c.ctxt.Diag("illegal argument: %v\n", p)
 			break
 		}
diff --git a/src/cmd/internal/obj/arm64/specialoperand_string.go b/src/cmd/internal/obj/arm64/specialoperand_string.go
index 0818649c93..0a73c69b12 100644
--- a/src/cmd/internal/obj/arm64/specialoperand_string.go
+++ b/src/cmd/internal/obj/arm64/specialoperand_string.go
@@ -105,30 +105,58 @@ func _() {
 	_ = x[SPOP_RVALE3OS-93]
 	_ = x[SPOP_RVAE3-94]
 	_ = x[SPOP_RVALE3-95]
-	_ = x[SPOP_DAIFSet-96]
-	_ = x[SPOP_DAIFClr-97]
-	_ = x[SPOP_EQ-98]
-	_ = x[SPOP_NE-99]
-	_ = x[SPOP_HS-100]
-	_ = x[SPOP_LO-101]
-	_ = x[SPOP_MI-102]
-	_ = x[SPOP_PL-103]
-	_ = x[SPOP_VS-104]
-	_ = x[SPOP_VC-105]
-	_ = x[SPOP_HI-106]
-	_ = x[SPOP_LS-107]
-	_ = x[SPOP_GE-108]
-	_ = x[SPOP_LT-109]
-	_ = x[SPOP_GT-110]
-	_ = x[SPOP_LE-111]
-	_ = x[SPOP_AL-112]
-	_ = x[SPOP_NV-113]
-	_ = x[SPOP_END-114]
+	_ = x[SPOP_IVAC-96]
+	_ = x[SPOP_ISW-97]
+	_ = x[SPOP_CSW-98]
+	_ = x[SPOP_CISW-99]
+	_ = x[SPOP_ZVA-100]
+	_ = x[SPOP_CVAC-101]
+	_ = x[SPOP_CVAU-102]
+	_ = x[SPOP_CIVAC-103]
+	_ = x[SPOP_IGVAC-104]
+	_ = x[SPOP_IGSW-105]
+	_ = x[SPOP_IGDVAC-106]
+	_ = x[SPOP_IGDSW-107]
+	_ = x[SPOP_CGSW-108]
+	_ = x[SPOP_CGDSW-109]
+	_ = x[SPOP_CIGSW-110]
+	_ = x[SPOP_CIGDSW-111]
+	_ = x[SPOP_GVA-112]
+	_ = x[SPOP_GZVA-113]
+	_ = x[SPOP_CGVAC-114]
+	_ = x[SPOP_CGDVAC-115]
+	_ = x[SPOP_CGVAP-116]
+	_ = x[SPOP_CGDVAP-117]
+	_ = x[SPOP_CGVADP-118]
+	_ = x[SPOP_CGDVADP-119]
+	_ = x[SPOP_CIGVAC-120]
+	_ = x[SPOP_CIGDVAC-121]
+	_ = x[SPOP_CVAP-122]
+	_ = x[SPOP_CVADP-123]
+	_ = x[SPOP_DAIFSet-124]
+	_ = x[SPOP_DAIFClr-125]
+	_ = x[SPOP_EQ-126]
+	_ = x[SPOP_NE-127]
+	_ = x[SPOP_HS-128]
+	_ = x[SPOP_LO-129]
+	_ = x[SPOP_MI-130]
+	_ = x[SPOP_PL-131]
+	_ = x[SPOP_VS-132]
+	_ = x[SPOP_VC-133]
+	_ = x[SPOP_HI-134]
+	_ = x[SPOP_LS-135]
+	_ = x[SPOP_GE-136]
+	_ = x[SPOP_LT-137]
+	_ = x[SPOP_GT-138]
+	_ = x[SPOP_LE-139]
+	_ = x[SPOP_AL-140]
+	_ = x[SPOP_NV-141]
+	_ = x[SPOP_END-142]
 }
 
-const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3DAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVEND"
+const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVEND"
 
-var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 171, 177, 185, 192, 199, 207, 214, 218, 224, 229, 234, 240, 249, 259, 266, 272, 279, 286, 298, 305, 313, 318, 322, 327, 332, 342, 349, 355, 362, 367, 371, 376, 385, 391, 399, 406, 413, 421, 428, 436, 444, 453, 460, 468, 476, 485, 490, 496, 502, 509, 519, 530, 537, 543, 550, 557, 569, 576, 584, 593, 601, 611, 621, 630, 641, 648, 656, 661, 667, 674, 680, 687, 694, 702, 709, 717, 722, 728, 735, 742, 744, 746, 748, 750, 752, 754, 756, 758, 760, 762, 764, 766, 768, 770, 772, 774, 777}
+var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 171, 177, 185, 192, 199, 207, 214, 218, 224, 229, 234, 240, 249, 259, 266, 272, 279, 286, 298, 305, 313, 318, 322, 327, 332, 342, 349, 355, 362, 367, 371, 376, 385, 391, 399, 406, 413, 421, 428, 436, 444, 453, 460, 468, 476, 485, 490, 496, 502, 509, 519, 530, 537, 543, 550, 557, 569, 576, 584, 593, 601, 611, 621, 630, 641, 648, 656, 661, 667, 674, 680, 687, 694, 702, 709, 717, 722, 728, 732, 735, 738, 742, 745, 749, 753, 758, 763, 767, 773, 778, 782, 787, 792, 798, 801, 805, 810, 816, 821, 827, 833, 840, 846, 853, 857, 862, 869, 876, 878, 880, 882, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 911}
 
 func (i SpecialOperand) String() string {
 	if i < 0 || i >= SpecialOperand(len(_SpecialOperand_index)-1) {