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| author | Alberto Donizetti <alb.donizetti@gmail.com> | 2020-10-28 10:10:55 +0100 |
|---|---|---|
| committer | Alberto Donizetti <alb.donizetti@gmail.com> | 2020-10-28 19:19:18 +0000 |
| commit | 1090f0986dd9d7e1f3c31a7f70f45d02ccf49964 (patch) | |
| tree | c9319051d9ad1b3e45374dd74720e387b366d3e7 | |
| parent | bc0d7fd9b7b2a8791441a07921b0c26b7b316b92 (diff) | |
| download | go-1090f0986dd9d7e1f3c31a7f70f45d02ccf49964.tar.gz go-1090f0986dd9d7e1f3c31a7f70f45d02ccf49964.zip | |
cmd/compile: rename mergeSymTyped to mergeSym
Also make canMergeSym take Syms instead of interface{}
Change-Id: I4926a1fc586aa90e198249d67e5b520404b40869
Reviewed-on: https://go-review.googlesource.com/c/go/+/265817
Trust: Alberto Donizetti <alb.donizetti@gmail.com>
Run-TryBot: Alberto Donizetti <alb.donizetti@gmail.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
19 files changed, 791 insertions, 801 deletions
diff --git a/src/cmd/compile/internal/ssa/gen/386.rules b/src/cmd/compile/internal/ssa/gen/386.rules index 4e6cc8c692..36a66d6bf1 100644 --- a/src/cmd/compile/internal/ssa/gen/386.rules +++ b/src/cmd/compile/internal/ssa/gen/386.rules @@ -640,31 +640,31 @@ // it compiles to a thunk call). (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOV(L|W|B|SS|SD)store [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - (MOV(L|W|B|SS|SD)store [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOV(L|W|B|SS|SD)store [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOV(L|W|B)storeconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOV(L|W|B)storeconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOV(L|W|B)storeconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) && valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => - ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) // Merge load/store to op ((ADD|AND|OR|XOR|SUB|MUL)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|AND|OR|XOR|SUB|MUL)Lload x [off] {sym} ptr mem) @@ -679,37 +679,37 @@ // fold LEALs together (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL [off1+off2] {mergeSymTyped(sym1,sym2)} x) + (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) // LEAL into LEAL1 (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAL1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAL1 into LEAL (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAL into LEAL[248] (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAL2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAL4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAL8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAL[248] into LEAL (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAL[1248] into LEAL[1248]. Only some such merges are possible. (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL2 [off1+off2] {mergeSymTyped(sym1, sym2)} x y) + (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} x y) (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAL2 [off1+off2] {mergeSymTyped(sym1, sym2)} y x) + (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} y x) (LEAL2 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+2*int64(off2)) => (LEAL4 [off1+2*off2] {sym} x y) (LEAL4 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+4*int64(off2)) => diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules index 4372f27c44..a866a967b9 100644 --- a/src/cmd/compile/internal/ssa/gen/AMD64.rules +++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules @@ -1137,80 +1137,80 @@ // what variables are being read/written by the ops. (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOV(Q|L|W|B)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) => - (MOV(Q|L|W|B)storeconst [ValAndOff(sc).addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOV(Q|L|W|B)storeconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {mergeSym(sym1,sym2)} base val mem) ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem) (CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (CMP(Q|L|W|B)load [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (CMP(Q|L|W|B)load [off1+off2] {mergeSym(sym1,sym2)} base val mem) (CMP(Q|L|W|B)constload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) => - (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) ((ADD|AND|OR|XOR|BTC|BTR|BTS)Qconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) => - ((ADD|AND|OR|XOR|BTC|BTR|BTS)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + ((ADD|AND|OR|XOR|BTC|BTR|BTS)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) ((ADD|AND|OR|XOR|BTC|BTR|BTS)Lconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) => - ((ADD|AND|OR|XOR|BTC|BTR|BTS)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + ((ADD|AND|OR|XOR|BTC|BTR|BTS)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Qmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Qmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Qmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Lmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Lmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + ((ADD|SUB|AND|OR|XOR|BTC|BTR|BTS)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) // fold LEAQs together (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ [off1+off2] {mergeSymTyped(sym1,sym2)} x) + (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) // LEAQ into LEAQ1 (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAQ1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAQ1 into LEAQ (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAQ into LEAQ[248] (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAQ2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAQ4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (LEAQ8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAQ[248] into LEAQ (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) // LEAQ[1248] into LEAQ[1248]. Only some such merges are possible. (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ2 [off1+off2] {mergeSymTyped(sym1, sym2)} x y) + (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (LEAQ2 [off1+off2] {mergeSymTyped(sym1, sym2)} y x) + (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil => (LEAQ4 [off1+2*off2] {sym1} x y) (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil => @@ -2000,31 +2000,31 @@ => (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVQload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVLload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVQstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVLstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVQstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVQstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVLstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVLstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVWstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVWstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVBstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVBstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (MOVQload [off1+off2] {sym} ptr mem) (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (MOVLload [off1+off2] {sym} ptr mem) @@ -2060,17 +2060,17 @@ (MOV(Q|L|B)atomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (MOV(Q|L|B)atomicload [off1+off2] {sym} ptr mem) (MOV(Q|L|B)atomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOV(Q|L|B)atomicload [off1+off2] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOV(Q|L|B)atomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) // Merge ADDQconst and LEAQ into atomic stores. (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (XCHGQ [off1+off2] {sym} val ptr mem) (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB => - (XCHGQ [off1+off2] {mergeSymTyped(sym1,sym2)} val ptr mem) + (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (XCHGL [off1+off2] {sym} val ptr mem) (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB => - (XCHGL [off1+off2] {mergeSymTyped(sym1,sym2)} val ptr mem) + (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) // Merge ADDQconst into atomic adds. // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions. diff --git a/src/cmd/compile/internal/ssa/gen/ARM.rules b/src/cmd/compile/internal/ssa/gen/ARM.rules index f48abcd202..946acd4ccc 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM.rules +++ b/src/cmd/compile/internal/ssa/gen/ARM.rules @@ -433,30 +433,30 @@ (MOVDstore [off1] {sym} (SUBconst [off2] ptr) val mem) => (MOVDstore [off1-off2] {sym} ptr val mem) (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x) diff --git a/src/cmd/compile/internal/ssa/gen/ARM64.rules b/src/cmd/compile/internal/ssa/gen/ARM64.rules index a4ca6f2d0c..7e014fe0a8 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM64.rules +++ b/src/cmd/compile/internal/ssa/gen/ARM64.rules @@ -861,88 +861,88 @@ (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVWUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (STP [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val1 val2 mem) + (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => - (MOVQstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // store zero (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem) diff --git a/src/cmd/compile/internal/ssa/gen/MIPS.rules b/src/cmd/compile/internal/ssa/gen/MIPS.rules index b6e5312224..aff12b4e36 100644 --- a/src/cmd/compile/internal/ssa/gen/MIPS.rules +++ b/src/cmd/compile/internal/ssa/gen/MIPS.rules @@ -462,36 +462,36 @@ (MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstorezero [off1+off2] {sym} ptr mem) (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => - (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x) diff --git a/src/cmd/compile/internal/ssa/gen/MIPS64.rules b/src/cmd/compile/internal/ssa/gen/MIPS64.rules index 25ca09c6aa..9af0f93333 100644 --- a/src/cmd/compile/internal/ssa/gen/MIPS64.rules +++ b/src/cmd/compile/internal/ssa/gen/MIPS64.rules @@ -462,44 +462,44 @@ (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVstorezero [off1+int32(off2)] {sym} ptr mem) (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVHload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVHUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVVload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVFload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVDload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVHstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVVstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVFstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVDstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVHstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVVstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) // store zero (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem) diff --git a/src/cmd/compile/internal/ssa/gen/PPC64.rules b/src/cmd/compile/internal/ssa/gen/PPC64.rules index 558b09c9f2..31b186d167 100644 --- a/src/cmd/compile/internal/ssa/gen/PPC64.rules +++ b/src/cmd/compile/internal/ssa/gen/PPC64.rules @@ -888,48 +888,48 @@ // is only one use. (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVBZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVHZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (MOVWZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) => - (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // Fold offsets for loads. (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is16Bit(int64(off1)+off2) => (FMOVSload [off1+int32(off2)] {sym} ptr mem) @@ -979,16 +979,16 @@ // Fold symbols into storezero (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 => - (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) => - (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) => - (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) => - (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) // atomic intrinsics (AtomicLoad(8|32|64|Ptr) ptr mem) => (LoweredAtomicLoad(8|32|64|Ptr) [1] ptr mem) diff --git a/src/cmd/compile/internal/ssa/gen/RISCV64.rules b/src/cmd/compile/internal/ssa/gen/RISCV64.rules index 325cbeb825..306103c7b6 100644 --- a/src/cmd/compile/internal/ssa/gen/RISCV64.rules +++ b/src/cmd/compile/internal/ssa/gen/RISCV64.rules @@ -289,36 +289,36 @@ // We need to fold MOVaddr into the LD/MOVDstore ops so that the live variable analysis // knows what variables are being read/written by the ops. (MOVBUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVBload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVHUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVHload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVWUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVWUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVWload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVDload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVBstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVHstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVWstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVDstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVBstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => - (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1] {sym} (ADDI [off2] base) mem) && is32Bit(int64(off1)+off2) => (MOVBUload [off1+int32(off2)] {sym} base mem) diff --git a/src/cmd/compile/internal/ssa/gen/S390X.rules b/src/cmd/compile/internal/ssa/gen/S390X.rules index 2d6f091a4e..1b56361c00 100644 --- a/src/cmd/compile/internal/ssa/gen/S390X.rules +++ b/src/cmd/compile/internal/ssa/gen/S390X.rules @@ -874,67 +874,67 @@ // loads/stores using PC-relative addressing directly must be aligned to the // size of the target. (MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%8 == 0 && (off1+off2)%8 == 0)) => - (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) => - (MOVWZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) => - (MOVHZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem) (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} base mem) (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) => - (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) => - (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) (MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%8 == 0 && (off1+off2)%8 == 0)) => - (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) => - (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) => - (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => - (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) - -(ADDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ADDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(ADDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ADDWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(MULLDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (MULLDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(MULLWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (MULLWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(SUBload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (SUBload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(SUBWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (SUBWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) - -(ANDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ANDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(ANDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ANDWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(ORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ORload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(ORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ORWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(XORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (XORload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) -(XORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (XORWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + +(ADDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ADDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(ADDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ADDWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(MULLDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (MULLDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(MULLWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (MULLWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(SUBload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (SUBload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(SUBWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (SUBWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) + +(ANDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ANDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(ANDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ANDWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(ORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ORload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(ORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (ORWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(XORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (XORload [o1+o2] {mergeSym(s1, s2)} x ptr mem) +(XORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) && ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) => (XORWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) // Cannot store constant to SB directly (no 'move relative long immediate' instructions). (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVDstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVDstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVWstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVWstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVHstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVHstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) => - (MOVBstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + (MOVBstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) // MOVDaddr into MOVDaddridx (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => - (MOVDaddridx [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && y.Op != OpSB => - (MOVDaddridx [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) // Absorb InvertFlags into branches. (BRC {c} (InvertFlags cmp) yes no) => (BRC {c.ReverseComparison()} cmp yes no) diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go index bae4f5057d..974c5ac8c3 100644 --- a/src/cmd/compile/internal/ssa/rewrite.go +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -212,30 +212,20 @@ func isSigned(t *types.Type) bool { // mergeSym merges two symbolic offsets. There is no real merging of // offsets, we just pick the non-nil one. -func mergeSym(x, y interface{}) interface{} { +func mergeSym(x, y Sym) Sym { if x == nil { return y } if y == nil { return x } - panic(fmt.Sprintf("mergeSym with two non-nil syms %s %s", x, y)) + panic(fmt.Sprintf("mergeSym with two non-nil syms %v %v", x, y)) } -func canMergeSym(x, y interface{}) bool { +func canMergeSym(x, y Sym) bool { return x == nil || y == nil } -func mergeSymTyped(x, y Sym) Sym { - if x == nil { - return y - } - if y == nil { - return x - } - panic(fmt.Sprintf("mergeSym with two non-nil syms %v %v", x, y)) -} - // canMergeLoadClobber reports whether the load can be merged into target without // invalidating the schedule. // It also checks that the other non-load argument x is something we diff --git a/src/cmd/compile/internal/ssa/rewrite386.go b/src/cmd/compile/internal/ssa/rewrite386.go index afce14fa76..b75dcc98fa 100644 --- a/src/cmd/compile/internal/ssa/rewrite386.go +++ b/src/cmd/compile/internal/ssa/rewrite386.go @@ -1179,7 +1179,7 @@ func rewriteValue386_Op386ADDLconstmodify(v *Value) bool { } // match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ADDLconstmodify [valoff1.addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ADDLconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1195,7 +1195,7 @@ func rewriteValue386_Op386ADDLconstmodify(v *Value) bool { } v.reset(Op386ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(valoff1.addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -1231,7 +1231,7 @@ func rewriteValue386_Op386ADDLload(v *Value) bool { } // match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ADDLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1248,7 +1248,7 @@ func rewriteValue386_Op386ADDLload(v *Value) bool { } v.reset(Op386ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -1284,7 +1284,7 @@ func rewriteValue386_Op386ADDLmodify(v *Value) bool { } // match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ADDLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1301,7 +1301,7 @@ func rewriteValue386_Op386ADDLmodify(v *Value) bool { } v.reset(Op386ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -1367,7 +1367,7 @@ func rewriteValue386_Op386ADDSDload(v *Value) bool { } // match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ADDSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1384,7 +1384,7 @@ func rewriteValue386_Op386ADDSDload(v *Value) bool { } v.reset(Op386ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -1450,7 +1450,7 @@ func rewriteValue386_Op386ADDSSload(v *Value) bool { } // match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ADDSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1467,7 +1467,7 @@ func rewriteValue386_Op386ADDSSload(v *Value) bool { } v.reset(Op386ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -1611,7 +1611,7 @@ func rewriteValue386_Op386ANDLconstmodify(v *Value) bool { } // match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ANDLconstmodify [valoff1.addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ANDLconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1627,7 +1627,7 @@ func rewriteValue386_Op386ANDLconstmodify(v *Value) bool { } v.reset(Op386ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(valoff1.addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -1663,7 +1663,7 @@ func rewriteValue386_Op386ANDLload(v *Value) bool { } // match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ANDLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1680,7 +1680,7 @@ func rewriteValue386_Op386ANDLload(v *Value) bool { } v.reset(Op386ANDLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -1716,7 +1716,7 @@ func rewriteValue386_Op386ANDLmodify(v *Value) bool { } // match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ANDLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1733,7 +1733,7 @@ func rewriteValue386_Op386ANDLmodify(v *Value) bool { } v.reset(Op386ANDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -2690,7 +2690,7 @@ func rewriteValue386_Op386DIVSDload(v *Value) bool { } // match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (DIVSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2707,7 +2707,7 @@ func rewriteValue386_Op386DIVSDload(v *Value) bool { } v.reset(Op386DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -2770,7 +2770,7 @@ func rewriteValue386_Op386DIVSSload(v *Value) bool { } // match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (DIVSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2787,7 +2787,7 @@ func rewriteValue386_Op386DIVSSload(v *Value) bool { } v.reset(Op386DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -2843,7 +2843,7 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } // match: (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL [off1+off2] {mergeSymTyped(sym1,sym2)} x) + // result: (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2858,13 +2858,13 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } v.reset(Op386LEAL) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2880,13 +2880,13 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } v.reset(Op386LEAL1) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2902,13 +2902,13 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } v.reset(Op386LEAL2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2924,13 +2924,13 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } v.reset(Op386LEAL4) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2946,7 +2946,7 @@ func rewriteValue386_Op386LEAL(v *Value) bool { } v.reset(Op386LEAL8) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3038,7 +3038,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } // match: (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAL1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3055,7 +3055,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } v.reset(Op386LEAL1) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3063,7 +3063,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } // match: (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL2 [off1+off2] {mergeSymTyped(sym1, sym2)} x y) + // result: (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3080,7 +3080,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } v.reset(Op386LEAL2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3088,7 +3088,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } // match: (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAL2 [off1+off2] {mergeSymTyped(sym1, sym2)} y x) + // result: (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3112,7 +3112,7 @@ func rewriteValue386_Op386LEAL1(v *Value) bool { } v.reset(Op386LEAL2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } @@ -3212,7 +3212,7 @@ func rewriteValue386_Op386LEAL2(v *Value) bool { } // match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAL2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3228,7 +3228,7 @@ func rewriteValue386_Op386LEAL2(v *Value) bool { } v.reset(Op386LEAL2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3321,7 +3321,7 @@ func rewriteValue386_Op386LEAL4(v *Value) bool { } // match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAL4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3337,7 +3337,7 @@ func rewriteValue386_Op386LEAL4(v *Value) bool { } v.reset(Op386LEAL4) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3414,7 +3414,7 @@ func rewriteValue386_Op386LEAL8(v *Value) bool { } // match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAL8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3430,7 +3430,7 @@ func rewriteValue386_Op386LEAL8(v *Value) bool { } v.reset(Op386LEAL8) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -3509,7 +3509,7 @@ func rewriteValue386_Op386MOVBLSXload(v *Value) bool { } // match: (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBLSXload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3525,7 +3525,7 @@ func rewriteValue386_Op386MOVBLSXload(v *Value) bool { } v.reset(Op386MOVBLSXload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3621,7 +3621,7 @@ func rewriteValue386_Op386MOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3637,7 +3637,7 @@ func rewriteValue386_Op386MOVBload(v *Value) bool { } v.reset(Op386MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3741,7 +3741,7 @@ func rewriteValue386_Op386MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3758,7 +3758,7 @@ func rewriteValue386_Op386MOVBstore(v *Value) bool { } v.reset(Op386MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4052,7 +4052,7 @@ func rewriteValue386_Op386MOVBstoreconst(v *Value) bool { } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4068,7 +4068,7 @@ func rewriteValue386_Op386MOVBstoreconst(v *Value) bool { } v.reset(Op386MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4224,7 +4224,7 @@ func rewriteValue386_Op386MOVLload(v *Value) bool { } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVLload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4240,7 +4240,7 @@ func rewriteValue386_Op386MOVLload(v *Value) bool { } v.reset(Op386MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4310,7 +4310,7 @@ func rewriteValue386_Op386MOVLstore(v *Value) bool { } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVLstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4327,7 +4327,7 @@ func rewriteValue386_Op386MOVLstore(v *Value) bool { } v.reset(Op386MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4719,7 +4719,7 @@ func rewriteValue386_Op386MOVLstoreconst(v *Value) bool { } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVLstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVLstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4735,7 +4735,7 @@ func rewriteValue386_Op386MOVLstoreconst(v *Value) bool { } v.reset(Op386MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4789,7 +4789,7 @@ func rewriteValue386_Op386MOVSDload(v *Value) bool { } // match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVSDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4805,7 +4805,7 @@ func rewriteValue386_Op386MOVSDload(v *Value) bool { } v.reset(Op386MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4841,7 +4841,7 @@ func rewriteValue386_Op386MOVSDstore(v *Value) bool { } // match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVSDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4858,7 +4858,7 @@ func rewriteValue386_Op386MOVSDstore(v *Value) bool { } v.reset(Op386MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4912,7 +4912,7 @@ func rewriteValue386_Op386MOVSSload(v *Value) bool { } // match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVSSload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4928,7 +4928,7 @@ func rewriteValue386_Op386MOVSSload(v *Value) bool { } v.reset(Op386MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4964,7 +4964,7 @@ func rewriteValue386_Op386MOVSSstore(v *Value) bool { } // match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVSSstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4981,7 +4981,7 @@ func rewriteValue386_Op386MOVSSstore(v *Value) bool { } v.reset(Op386MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -5060,7 +5060,7 @@ func rewriteValue386_Op386MOVWLSXload(v *Value) bool { } // match: (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWLSXload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5076,7 +5076,7 @@ func rewriteValue386_Op386MOVWLSXload(v *Value) bool { } v.reset(Op386MOVWLSXload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -5172,7 +5172,7 @@ func rewriteValue386_Op386MOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5188,7 +5188,7 @@ func rewriteValue386_Op386MOVWload(v *Value) bool { } v.reset(Op386MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -5292,7 +5292,7 @@ func rewriteValue386_Op386MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5309,7 +5309,7 @@ func rewriteValue386_Op386MOVWstore(v *Value) bool { } v.reset(Op386MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -5452,7 +5452,7 @@ func rewriteValue386_Op386MOVWstoreconst(v *Value) bool { } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5468,7 +5468,7 @@ func rewriteValue386_Op386MOVWstoreconst(v *Value) bool { } v.reset(Op386MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -6070,7 +6070,7 @@ func rewriteValue386_Op386MULLload(v *Value) bool { } // match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MULLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (MULLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6087,7 +6087,7 @@ func rewriteValue386_Op386MULLload(v *Value) bool { } v.reset(Op386MULLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -6153,7 +6153,7 @@ func rewriteValue386_Op386MULSDload(v *Value) bool { } // match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MULSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6170,7 +6170,7 @@ func rewriteValue386_Op386MULSDload(v *Value) bool { } v.reset(Op386MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -6236,7 +6236,7 @@ func rewriteValue386_Op386MULSSload(v *Value) bool { } // match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MULSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6253,7 +6253,7 @@ func rewriteValue386_Op386MULSSload(v *Value) bool { } v.reset(Op386MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -6686,7 +6686,7 @@ func rewriteValue386_Op386ORLconstmodify(v *Value) bool { } // match: (ORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ORLconstmodify [valoff1.addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ORLconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6702,7 +6702,7 @@ func rewriteValue386_Op386ORLconstmodify(v *Value) bool { } v.reset(Op386ORLconstmodify) v.AuxInt = valAndOffToAuxInt(valoff1.addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -6738,7 +6738,7 @@ func rewriteValue386_Op386ORLload(v *Value) bool { } // match: (ORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ORLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6755,7 +6755,7 @@ func rewriteValue386_Op386ORLload(v *Value) bool { } v.reset(Op386ORLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -6791,7 +6791,7 @@ func rewriteValue386_Op386ORLmodify(v *Value) bool { } // match: (ORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (ORLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6808,7 +6808,7 @@ func rewriteValue386_Op386ORLmodify(v *Value) bool { } v.reset(Op386ORLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8096,7 +8096,7 @@ func rewriteValue386_Op386SUBLload(v *Value) bool { } // match: (SUBLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (SUBLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8113,7 +8113,7 @@ func rewriteValue386_Op386SUBLload(v *Value) bool { } v.reset(Op386SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -8149,7 +8149,7 @@ func rewriteValue386_Op386SUBLmodify(v *Value) bool { } // match: (SUBLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (SUBLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8166,7 +8166,7 @@ func rewriteValue386_Op386SUBLmodify(v *Value) bool { } v.reset(Op386SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8229,7 +8229,7 @@ func rewriteValue386_Op386SUBSDload(v *Value) bool { } // match: (SUBSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (SUBSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8246,7 +8246,7 @@ func rewriteValue386_Op386SUBSDload(v *Value) bool { } v.reset(Op386SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -8309,7 +8309,7 @@ func rewriteValue386_Op386SUBSSload(v *Value) bool { } // match: (SUBSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (SUBSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8326,7 +8326,7 @@ func rewriteValue386_Op386SUBSSload(v *Value) bool { } v.reset(Op386SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -8533,7 +8533,7 @@ func rewriteValue386_Op386XORLconstmodify(v *Value) bool { } // match: (XORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (XORLconstmodify [valoff1.addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (XORLconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8549,7 +8549,7 @@ func rewriteValue386_Op386XORLconstmodify(v *Value) bool { } v.reset(Op386XORLconstmodify) v.AuxInt = valAndOffToAuxInt(valoff1.addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -8585,7 +8585,7 @@ func rewriteValue386_Op386XORLload(v *Value) bool { } // match: (XORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (XORLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8602,7 +8602,7 @@ func rewriteValue386_Op386XORLload(v *Value) bool { } v.reset(Op386XORLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -8638,7 +8638,7 @@ func rewriteValue386_Op386XORLmodify(v *Value) bool { } // match: (XORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) - // result: (XORLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8655,7 +8655,7 @@ func rewriteValue386_Op386XORLmodify(v *Value) bool { } v.reset(Op386XORLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index eae316dbe4..75d4ff7357 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -1702,7 +1702,7 @@ func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1718,7 +1718,7 @@ func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -1754,7 +1754,7 @@ func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1771,7 +1771,7 @@ func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -1825,7 +1825,7 @@ func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -1842,7 +1842,7 @@ func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -2318,7 +2318,7 @@ func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2334,7 +2334,7 @@ func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -2370,7 +2370,7 @@ func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDQload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2387,7 +2387,7 @@ func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -2441,7 +2441,7 @@ func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2458,7 +2458,7 @@ func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -2524,7 +2524,7 @@ func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2541,7 +2541,7 @@ func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -2627,7 +2627,7 @@ func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ADDSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2644,7 +2644,7 @@ func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -2899,7 +2899,7 @@ func rewriteValueAMD64_OpAMD64ANDLconstmodify(v *Value) bool { } // match: (ANDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ANDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ANDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2915,7 +2915,7 @@ func rewriteValueAMD64_OpAMD64ANDLconstmodify(v *Value) bool { } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -2951,7 +2951,7 @@ func rewriteValueAMD64_OpAMD64ANDLload(v *Value) bool { } // match: (ANDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ANDLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2968,7 +2968,7 @@ func rewriteValueAMD64_OpAMD64ANDLload(v *Value) bool { } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -3022,7 +3022,7 @@ func rewriteValueAMD64_OpAMD64ANDLmodify(v *Value) bool { } // match: (ANDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ANDLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3039,7 +3039,7 @@ func rewriteValueAMD64_OpAMD64ANDLmodify(v *Value) bool { } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3278,7 +3278,7 @@ func rewriteValueAMD64_OpAMD64ANDQconstmodify(v *Value) bool { } // match: (ANDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ANDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ANDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3294,7 +3294,7 @@ func rewriteValueAMD64_OpAMD64ANDQconstmodify(v *Value) bool { } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3330,7 +3330,7 @@ func rewriteValueAMD64_OpAMD64ANDQload(v *Value) bool { } // match: (ANDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ANDQload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ANDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3347,7 +3347,7 @@ func rewriteValueAMD64_OpAMD64ANDQload(v *Value) bool { } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -3401,7 +3401,7 @@ func rewriteValueAMD64_OpAMD64ANDQmodify(v *Value) bool { } // match: (ANDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ANDQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ANDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3418,7 +3418,7 @@ func rewriteValueAMD64_OpAMD64ANDQmodify(v *Value) bool { } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3543,7 +3543,7 @@ func rewriteValueAMD64_OpAMD64BTCLconstmodify(v *Value) bool { } // match: (BTCLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTCLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTCLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3559,7 +3559,7 @@ func rewriteValueAMD64_OpAMD64BTCLconstmodify(v *Value) bool { } v.reset(OpAMD64BTCLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3593,7 +3593,7 @@ func rewriteValueAMD64_OpAMD64BTCLmodify(v *Value) bool { } // match: (BTCLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTCLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTCLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3610,7 +3610,7 @@ func rewriteValueAMD64_OpAMD64BTCLmodify(v *Value) bool { } v.reset(OpAMD64BTCLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3694,7 +3694,7 @@ func rewriteValueAMD64_OpAMD64BTCQconstmodify(v *Value) bool { } // match: (BTCQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTCQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTCQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3710,7 +3710,7 @@ func rewriteValueAMD64_OpAMD64BTCQconstmodify(v *Value) bool { } v.reset(OpAMD64BTCQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3744,7 +3744,7 @@ func rewriteValueAMD64_OpAMD64BTCQmodify(v *Value) bool { } // match: (BTCQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTCQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTCQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3761,7 +3761,7 @@ func rewriteValueAMD64_OpAMD64BTCQmodify(v *Value) bool { } v.reset(OpAMD64BTCQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4027,7 +4027,7 @@ func rewriteValueAMD64_OpAMD64BTRLconstmodify(v *Value) bool { } // match: (BTRLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTRLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTRLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4043,7 +4043,7 @@ func rewriteValueAMD64_OpAMD64BTRLconstmodify(v *Value) bool { } v.reset(OpAMD64BTRLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4077,7 +4077,7 @@ func rewriteValueAMD64_OpAMD64BTRLmodify(v *Value) bool { } // match: (BTRLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTRLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTRLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4094,7 +4094,7 @@ func rewriteValueAMD64_OpAMD64BTRLmodify(v *Value) bool { } v.reset(OpAMD64BTRLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4204,7 +4204,7 @@ func rewriteValueAMD64_OpAMD64BTRQconstmodify(v *Value) bool { } // match: (BTRQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTRQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTRQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4220,7 +4220,7 @@ func rewriteValueAMD64_OpAMD64BTRQconstmodify(v *Value) bool { } v.reset(OpAMD64BTRQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4254,7 +4254,7 @@ func rewriteValueAMD64_OpAMD64BTRQmodify(v *Value) bool { } // match: (BTRQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTRQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTRQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4271,7 +4271,7 @@ func rewriteValueAMD64_OpAMD64BTRQmodify(v *Value) bool { } v.reset(OpAMD64BTRQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4373,7 +4373,7 @@ func rewriteValueAMD64_OpAMD64BTSLconstmodify(v *Value) bool { } // match: (BTSLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTSLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTSLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4389,7 +4389,7 @@ func rewriteValueAMD64_OpAMD64BTSLconstmodify(v *Value) bool { } v.reset(OpAMD64BTSLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4423,7 +4423,7 @@ func rewriteValueAMD64_OpAMD64BTSLmodify(v *Value) bool { } // match: (BTSLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTSLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTSLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4440,7 +4440,7 @@ func rewriteValueAMD64_OpAMD64BTSLmodify(v *Value) bool { } v.reset(OpAMD64BTSLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -4550,7 +4550,7 @@ func rewriteValueAMD64_OpAMD64BTSQconstmodify(v *Value) bool { } // match: (BTSQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (BTSQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (BTSQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4566,7 +4566,7 @@ func rewriteValueAMD64_OpAMD64BTSQconstmodify(v *Value) bool { } v.reset(OpAMD64BTSQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -4600,7 +4600,7 @@ func rewriteValueAMD64_OpAMD64BTSQmodify(v *Value) bool { } // match: (BTSQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (BTSQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (BTSQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4617,7 +4617,7 @@ func rewriteValueAMD64_OpAMD64BTSQmodify(v *Value) bool { } v.reset(OpAMD64BTSQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -7008,7 +7008,7 @@ func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7024,7 +7024,7 @@ func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -7058,7 +7058,7 @@ func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPBload [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7075,7 +7075,7 @@ func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -7409,7 +7409,7 @@ func rewriteValueAMD64_OpAMD64CMPLconstload(v *Value) bool { } // match: (CMPLconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPLconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (CMPLconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7425,7 +7425,7 @@ func rewriteValueAMD64_OpAMD64CMPLconstload(v *Value) bool { } v.reset(OpAMD64CMPLconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -7459,7 +7459,7 @@ func rewriteValueAMD64_OpAMD64CMPLload(v *Value) bool { } // match: (CMPLload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPLload [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (CMPLload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7476,7 +7476,7 @@ func rewriteValueAMD64_OpAMD64CMPLload(v *Value) bool { } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -7979,7 +7979,7 @@ func rewriteValueAMD64_OpAMD64CMPQconstload(v *Value) bool { } // match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPQconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (CMPQconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7995,7 +7995,7 @@ func rewriteValueAMD64_OpAMD64CMPQconstload(v *Value) bool { } v.reset(OpAMD64CMPQconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -8029,7 +8029,7 @@ func rewriteValueAMD64_OpAMD64CMPQload(v *Value) bool { } // match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPQload [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (CMPQload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8046,7 +8046,7 @@ func rewriteValueAMD64_OpAMD64CMPQload(v *Value) bool { } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8365,7 +8365,7 @@ func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8381,7 +8381,7 @@ func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -8415,7 +8415,7 @@ func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPWload [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8432,7 +8432,7 @@ func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8574,7 +8574,7 @@ func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (DIVSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8591,7 +8591,7 @@ func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -8652,7 +8652,7 @@ func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (DIVSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8669,7 +8669,7 @@ func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -9122,7 +9122,7 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ [off1+off2] {mergeSymTyped(sym1,sym2)} x) + // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9137,13 +9137,13 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9159,13 +9159,13 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9181,13 +9181,13 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9203,13 +9203,13 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9225,7 +9225,7 @@ func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9317,7 +9317,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ1 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9334,7 +9334,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9342,7 +9342,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSymTyped(sym1, sym2)} x y) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9359,7 +9359,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9367,7 +9367,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSymTyped(sym1, sym2)} y x) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9391,7 +9391,7 @@ func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } @@ -9495,7 +9495,7 @@ func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ2 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9511,7 +9511,7 @@ func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9642,7 +9642,7 @@ func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ4 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9658,7 +9658,7 @@ func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9773,7 +9773,7 @@ func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ8 [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9789,7 +9789,7 @@ func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9986,7 +9986,7 @@ func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBQSXload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10002,7 +10002,7 @@ func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -10166,7 +10166,7 @@ func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBatomicload [off1+off2] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10182,7 +10182,7 @@ func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -10235,7 +10235,7 @@ func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10251,13 +10251,13 @@ func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10273,7 +10273,7 @@ func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -10631,7 +10631,7 @@ func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10648,7 +10648,7 @@ func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -11454,7 +11454,7 @@ func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11471,7 +11471,7 @@ func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -11525,7 +11525,7 @@ func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11541,7 +11541,7 @@ func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -11597,7 +11597,7 @@ func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11613,7 +11613,7 @@ func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -11767,7 +11767,7 @@ func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLQSXload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11783,7 +11783,7 @@ func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -11923,7 +11923,7 @@ func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLatomicload [off1+off2] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11939,7 +11939,7 @@ func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -12046,7 +12046,7 @@ func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12062,13 +12062,13 @@ func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVLload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12084,7 +12084,7 @@ func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -12239,7 +12239,7 @@ func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12256,7 +12256,7 @@ func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -12412,7 +12412,7 @@ func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVLstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12429,7 +12429,7 @@ func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -13023,7 +13023,7 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13039,7 +13039,7 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -13099,7 +13099,7 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVLstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVLstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13115,7 +13115,7 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -13168,7 +13168,7 @@ func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVOload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13184,7 +13184,7 @@ func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -13221,7 +13221,7 @@ func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVOstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13238,7 +13238,7 @@ func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -13304,7 +13304,7 @@ func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVQatomicload [off1+off2] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13320,7 +13320,7 @@ func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -13426,7 +13426,7 @@ func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVQload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13442,13 +13442,13 @@ func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVQload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13464,7 +13464,7 @@ func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -13570,7 +13570,7 @@ func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVQstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13587,13 +13587,13 @@ func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVQstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13610,7 +13610,7 @@ func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -14204,7 +14204,7 @@ func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14220,7 +14220,7 @@ func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -14253,7 +14253,7 @@ func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { } // match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVQstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVQstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14269,7 +14269,7 @@ func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -14322,7 +14322,7 @@ func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVSDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14338,7 +14338,7 @@ func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -14389,7 +14389,7 @@ func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVSDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14406,7 +14406,7 @@ func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -14455,7 +14455,7 @@ func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVSSload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14471,7 +14471,7 @@ func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -14522,7 +14522,7 @@ func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVSSstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14539,7 +14539,7 @@ func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -14701,7 +14701,7 @@ func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWQSXload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14717,7 +14717,7 @@ func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -14892,7 +14892,7 @@ func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14908,13 +14908,13 @@ func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14930,7 +14930,7 @@ func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -15068,7 +15068,7 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -15085,7 +15085,7 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -15350,7 +15350,7 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -15367,7 +15367,7 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -15421,7 +15421,7 @@ func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -15437,7 +15437,7 @@ func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -15493,7 +15493,7 @@ func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -15509,7 +15509,7 @@ func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -16499,7 +16499,7 @@ func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MULSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -16516,7 +16516,7 @@ func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -16602,7 +16602,7 @@ func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MULSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -16619,7 +16619,7 @@ func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -18253,7 +18253,7 @@ func rewriteValueAMD64_OpAMD64ORLconstmodify(v *Value) bool { } // match: (ORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18269,7 +18269,7 @@ func rewriteValueAMD64_OpAMD64ORLconstmodify(v *Value) bool { } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -18305,7 +18305,7 @@ func rewriteValueAMD64_OpAMD64ORLload(v *Value) bool { } // match: (ORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18322,7 +18322,7 @@ func rewriteValueAMD64_OpAMD64ORLload(v *Value) bool { } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -18376,7 +18376,7 @@ func rewriteValueAMD64_OpAMD64ORLmodify(v *Value) bool { } // match: (ORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18393,7 +18393,7 @@ func rewriteValueAMD64_OpAMD64ORLmodify(v *Value) bool { } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -19880,7 +19880,7 @@ func rewriteValueAMD64_OpAMD64ORQconstmodify(v *Value) bool { } // match: (ORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -19896,7 +19896,7 @@ func rewriteValueAMD64_OpAMD64ORQconstmodify(v *Value) bool { } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -19932,7 +19932,7 @@ func rewriteValueAMD64_OpAMD64ORQload(v *Value) bool { } // match: (ORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORQload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (ORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -19949,7 +19949,7 @@ func rewriteValueAMD64_OpAMD64ORQload(v *Value) bool { } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -20003,7 +20003,7 @@ func rewriteValueAMD64_OpAMD64ORQmodify(v *Value) bool { } // match: (ORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (ORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -20020,7 +20020,7 @@ func rewriteValueAMD64_OpAMD64ORQmodify(v *Value) bool { } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -21531,7 +21531,7 @@ func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETAEstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -21548,7 +21548,7 @@ func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -21691,7 +21691,7 @@ func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETAstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -21708,7 +21708,7 @@ func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -22061,7 +22061,7 @@ func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETBEstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -22078,7 +22078,7 @@ func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -22221,7 +22221,7 @@ func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -22238,7 +22238,7 @@ func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -23213,7 +23213,7 @@ func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETEQstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -23230,7 +23230,7 @@ func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -23503,7 +23503,7 @@ func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETGEstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -23520,7 +23520,7 @@ func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -23663,7 +23663,7 @@ func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETGstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -23680,7 +23680,7 @@ func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -23953,7 +23953,7 @@ func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETLEstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -23970,7 +23970,7 @@ func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -24113,7 +24113,7 @@ func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETLstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -24130,7 +24130,7 @@ func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -25129,7 +25129,7 @@ func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETNEstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -25146,7 +25146,7 @@ func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -26454,7 +26454,7 @@ func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -26471,7 +26471,7 @@ func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -26525,7 +26525,7 @@ func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -26542,7 +26542,7 @@ func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -26733,7 +26733,7 @@ func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBQload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -26750,7 +26750,7 @@ func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -26804,7 +26804,7 @@ func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -26821,7 +26821,7 @@ func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -26884,7 +26884,7 @@ func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBSDload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -26901,7 +26901,7 @@ func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -26984,7 +26984,7 @@ func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBSSload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -27001,7 +27001,7 @@ func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -27465,7 +27465,7 @@ func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB - // result: (XCHGL [off1+off2] {mergeSymTyped(sym1,sym2)} val ptr mem) + // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -27482,7 +27482,7 @@ func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } @@ -27516,7 +27516,7 @@ func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB - // result: (XCHGQ [off1+off2] {mergeSymTyped(sym1,sym2)} val ptr mem) + // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -27533,7 +27533,7 @@ func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } @@ -27915,7 +27915,7 @@ func rewriteValueAMD64_OpAMD64XORLconstmodify(v *Value) bool { } // match: (XORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -27931,7 +27931,7 @@ func rewriteValueAMD64_OpAMD64XORLconstmodify(v *Value) bool { } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -27967,7 +27967,7 @@ func rewriteValueAMD64_OpAMD64XORLload(v *Value) bool { } // match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORLload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -27984,7 +27984,7 @@ func rewriteValueAMD64_OpAMD64XORLload(v *Value) bool { } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -28038,7 +28038,7 @@ func rewriteValueAMD64_OpAMD64XORLmodify(v *Value) bool { } // match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORLmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -28055,7 +28055,7 @@ func rewriteValueAMD64_OpAMD64XORLmodify(v *Value) bool { } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -28283,7 +28283,7 @@ func rewriteValueAMD64_OpAMD64XORQconstmodify(v *Value) bool { } // match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSymTyped(sym1,sym2)} base mem) + // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -28299,7 +28299,7 @@ func rewriteValueAMD64_OpAMD64XORQconstmodify(v *Value) bool { } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -28335,7 +28335,7 @@ func rewriteValueAMD64_OpAMD64XORQload(v *Value) bool { } // match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORQload [off1+off2] {mergeSymTyped(sym1,sym2)} val base mem) + // result: (XORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -28352,7 +28352,7 @@ func rewriteValueAMD64_OpAMD64XORQload(v *Value) bool { } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } @@ -28406,7 +28406,7 @@ func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool { } // match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORQmodify [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (XORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -28423,7 +28423,7 @@ func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool { } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go index 6ade8283d6..47fd0a94cc 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM.go +++ b/src/cmd/compile/internal/ssa/rewriteARM.go @@ -4529,7 +4529,7 @@ func rewriteValueARM_OpARMMOVBUload(v *Value) bool { } // match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4545,7 +4545,7 @@ func rewriteValueARM_OpARMMOVBUload(v *Value) bool { } v.reset(OpARMMOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4747,7 +4747,7 @@ func rewriteValueARM_OpARMMOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4763,7 +4763,7 @@ func rewriteValueARM_OpARMMOVBload(v *Value) bool { } v.reset(OpARMMOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4959,7 +4959,7 @@ func rewriteValueARM_OpARMMOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4976,7 +4976,7 @@ func rewriteValueARM_OpARMMOVBstore(v *Value) bool { } v.reset(OpARMMOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -5148,7 +5148,7 @@ func rewriteValueARM_OpARMMOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5164,7 +5164,7 @@ func rewriteValueARM_OpARMMOVDload(v *Value) bool { } v.reset(OpARMMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5232,7 +5232,7 @@ func rewriteValueARM_OpARMMOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5249,7 +5249,7 @@ func rewriteValueARM_OpARMMOVDstore(v *Value) bool { } v.reset(OpARMMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -5294,7 +5294,7 @@ func rewriteValueARM_OpARMMOVFload(v *Value) bool { } // match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5310,7 +5310,7 @@ func rewriteValueARM_OpARMMOVFload(v *Value) bool { } v.reset(OpARMMOVFload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5378,7 +5378,7 @@ func rewriteValueARM_OpARMMOVFstore(v *Value) bool { } // match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5395,7 +5395,7 @@ func rewriteValueARM_OpARMMOVFstore(v *Value) bool { } v.reset(OpARMMOVFstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -5442,7 +5442,7 @@ func rewriteValueARM_OpARMMOVHUload(v *Value) bool { } // match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5458,7 +5458,7 @@ func rewriteValueARM_OpARMMOVHUload(v *Value) bool { } v.reset(OpARMMOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5682,7 +5682,7 @@ func rewriteValueARM_OpARMMOVHload(v *Value) bool { } // match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5698,7 +5698,7 @@ func rewriteValueARM_OpARMMOVHload(v *Value) bool { } v.reset(OpARMMOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5938,7 +5938,7 @@ func rewriteValueARM_OpARMMOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5955,7 +5955,7 @@ func rewriteValueARM_OpARMMOVHstore(v *Value) bool { } v.reset(OpARMMOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -6095,7 +6095,7 @@ func rewriteValueARM_OpARMMOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6111,7 +6111,7 @@ func rewriteValueARM_OpARMMOVWload(v *Value) bool { } v.reset(OpARMMOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -6570,7 +6570,7 @@ func rewriteValueARM_OpARMMOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6587,7 +6587,7 @@ func rewriteValueARM_OpARMMOVWstore(v *Value) bool { } v.reset(OpARMMOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go index 0511d868cf..9a5e976dea 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64.go @@ -3872,7 +3872,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3888,7 +3888,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4003,7 +4003,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4020,7 +4020,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -4135,7 +4135,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4151,7 +4151,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4266,7 +4266,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4283,7 +4283,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -6228,7 +6228,7 @@ func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { } // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6244,7 +6244,7 @@ func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -6497,7 +6497,7 @@ func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6513,7 +6513,7 @@ func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -6714,7 +6714,7 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6731,7 +6731,7 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -8546,7 +8546,7 @@ func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { } // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8562,7 +8562,7 @@ func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -8792,7 +8792,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8808,7 +8808,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9089,7 +9089,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9106,7 +9106,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -9281,7 +9281,7 @@ func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { } // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9297,7 +9297,7 @@ func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9591,7 +9591,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { } // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9607,7 +9607,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9998,7 +9998,7 @@ func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { } // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10014,7 +10014,7 @@ func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -10399,7 +10399,7 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10416,7 +10416,7 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -11236,7 +11236,7 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { } // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11252,7 +11252,7 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -11558,7 +11558,7 @@ func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { } // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVQstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11574,7 +11574,7 @@ func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -11663,7 +11663,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { } // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11679,7 +11679,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -12095,7 +12095,7 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12111,7 +12111,7 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -12571,7 +12571,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -12588,7 +12588,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -13078,7 +13078,7 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { } // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13094,7 +13094,7 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -19632,7 +19632,7 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool { } // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) - // result: (STP [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val1 val2 mem) + // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -19650,7 +19650,7 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool { } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg4(ptr, val1, val2, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS.go b/src/cmd/compile/internal/ssa/rewriteMIPS.go index 0f0954fb83..970bd7b52e 100644 --- a/src/cmd/compile/internal/ssa/rewriteMIPS.go +++ b/src/cmd/compile/internal/ssa/rewriteMIPS.go @@ -2339,7 +2339,7 @@ func rewriteValueMIPS_OpMIPSMOVBUload(v *Value) bool { } // match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2355,7 +2355,7 @@ func rewriteValueMIPS_OpMIPSMOVBUload(v *Value) bool { } v.reset(OpMIPSMOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2484,7 +2484,7 @@ func rewriteValueMIPS_OpMIPSMOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2500,7 +2500,7 @@ func rewriteValueMIPS_OpMIPSMOVBload(v *Value) bool { } v.reset(OpMIPSMOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2635,7 +2635,7 @@ func rewriteValueMIPS_OpMIPSMOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2652,7 +2652,7 @@ func rewriteValueMIPS_OpMIPSMOVBstore(v *Value) bool { } v.reset(OpMIPSMOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -2786,7 +2786,7 @@ func rewriteValueMIPS_OpMIPSMOVBstorezero(v *Value) bool { } // match: (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2802,7 +2802,7 @@ func rewriteValueMIPS_OpMIPSMOVBstorezero(v *Value) bool { } v.reset(OpMIPSMOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2835,7 +2835,7 @@ func rewriteValueMIPS_OpMIPSMOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2851,7 +2851,7 @@ func rewriteValueMIPS_OpMIPSMOVDload(v *Value) bool { } v.reset(OpMIPSMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2906,7 +2906,7 @@ func rewriteValueMIPS_OpMIPSMOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2923,7 +2923,7 @@ func rewriteValueMIPS_OpMIPSMOVDstore(v *Value) bool { } v.reset(OpMIPSMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -2956,7 +2956,7 @@ func rewriteValueMIPS_OpMIPSMOVFload(v *Value) bool { } // match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2972,7 +2972,7 @@ func rewriteValueMIPS_OpMIPSMOVFload(v *Value) bool { } v.reset(OpMIPSMOVFload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3027,7 +3027,7 @@ func rewriteValueMIPS_OpMIPSMOVFstore(v *Value) bool { } // match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3044,7 +3044,7 @@ func rewriteValueMIPS_OpMIPSMOVFstore(v *Value) bool { } v.reset(OpMIPSMOVFstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3077,7 +3077,7 @@ func rewriteValueMIPS_OpMIPSMOVHUload(v *Value) bool { } // match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3093,7 +3093,7 @@ func rewriteValueMIPS_OpMIPSMOVHUload(v *Value) bool { } v.reset(OpMIPSMOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3244,7 +3244,7 @@ func rewriteValueMIPS_OpMIPSMOVHload(v *Value) bool { } // match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3260,7 +3260,7 @@ func rewriteValueMIPS_OpMIPSMOVHload(v *Value) bool { } v.reset(OpMIPSMOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3439,7 +3439,7 @@ func rewriteValueMIPS_OpMIPSMOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3456,7 +3456,7 @@ func rewriteValueMIPS_OpMIPSMOVHstore(v *Value) bool { } v.reset(OpMIPSMOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3556,7 +3556,7 @@ func rewriteValueMIPS_OpMIPSMOVHstorezero(v *Value) bool { } // match: (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3572,7 +3572,7 @@ func rewriteValueMIPS_OpMIPSMOVHstorezero(v *Value) bool { } v.reset(OpMIPSMOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3605,7 +3605,7 @@ func rewriteValueMIPS_OpMIPSMOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3621,7 +3621,7 @@ func rewriteValueMIPS_OpMIPSMOVWload(v *Value) bool { } v.reset(OpMIPSMOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3703,7 +3703,7 @@ func rewriteValueMIPS_OpMIPSMOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3720,7 +3720,7 @@ func rewriteValueMIPS_OpMIPSMOVWstore(v *Value) bool { } v.reset(OpMIPSMOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3786,7 +3786,7 @@ func rewriteValueMIPS_OpMIPSMOVWstorezero(v *Value) bool { } // match: (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3802,7 +3802,7 @@ func rewriteValueMIPS_OpMIPSMOVWstorezero(v *Value) bool { } v.reset(OpMIPSMOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS64.go b/src/cmd/compile/internal/ssa/rewriteMIPS64.go index 4b4e0ed35e..29e3a8a363 100644 --- a/src/cmd/compile/internal/ssa/rewriteMIPS64.go +++ b/src/cmd/compile/internal/ssa/rewriteMIPS64.go @@ -2558,7 +2558,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBUload(v *Value) bool { } // match: (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2574,7 +2574,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBUload(v *Value) bool { } v.reset(OpMIPS64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2643,7 +2643,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2659,7 +2659,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBload(v *Value) bool { } v.reset(OpMIPS64MOVBload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2730,7 +2730,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2747,7 +2747,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBstore(v *Value) bool { } v.reset(OpMIPS64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -2897,7 +2897,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBstorezero(v *Value) bool { } // match: (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2913,7 +2913,7 @@ func rewriteValueMIPS64_OpMIPS64MOVBstorezero(v *Value) bool { } v.reset(OpMIPS64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2945,7 +2945,7 @@ func rewriteValueMIPS64_OpMIPS64MOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVDload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2961,7 +2961,7 @@ func rewriteValueMIPS64_OpMIPS64MOVDload(v *Value) bool { } v.reset(OpMIPS64MOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2995,7 +2995,7 @@ func rewriteValueMIPS64_OpMIPS64MOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVDstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3012,7 +3012,7 @@ func rewriteValueMIPS64_OpMIPS64MOVDstore(v *Value) bool { } v.reset(OpMIPS64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3044,7 +3044,7 @@ func rewriteValueMIPS64_OpMIPS64MOVFload(v *Value) bool { } // match: (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVFload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3060,7 +3060,7 @@ func rewriteValueMIPS64_OpMIPS64MOVFload(v *Value) bool { } v.reset(OpMIPS64MOVFload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3094,7 +3094,7 @@ func rewriteValueMIPS64_OpMIPS64MOVFstore(v *Value) bool { } // match: (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVFstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3111,7 +3111,7 @@ func rewriteValueMIPS64_OpMIPS64MOVFstore(v *Value) bool { } v.reset(OpMIPS64MOVFstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3143,7 +3143,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHUload(v *Value) bool { } // match: (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVHUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3159,7 +3159,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHUload(v *Value) bool { } v.reset(OpMIPS64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3250,7 +3250,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHload(v *Value) bool { } // match: (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVHload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3266,7 +3266,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHload(v *Value) bool { } v.reset(OpMIPS64MOVHload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3381,7 +3381,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVHstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3398,7 +3398,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHstore(v *Value) bool { } v.reset(OpMIPS64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3514,7 +3514,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHstorezero(v *Value) bool { } // match: (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVHstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3530,7 +3530,7 @@ func rewriteValueMIPS64_OpMIPS64MOVHstorezero(v *Value) bool { } v.reset(OpMIPS64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3562,7 +3562,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVload(v *Value) bool { } // match: (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVVload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3578,7 +3578,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVload(v *Value) bool { } v.reset(OpMIPS64MOVVload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3639,7 +3639,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVstore(v *Value) bool { } // match: (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVVstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3656,7 +3656,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVstore(v *Value) bool { } v.reset(OpMIPS64MOVVstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -3704,7 +3704,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVstorezero(v *Value) bool { } // match: (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVVstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3720,7 +3720,7 @@ func rewriteValueMIPS64_OpMIPS64MOVVstorezero(v *Value) bool { } v.reset(OpMIPS64MOVVstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3752,7 +3752,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWUload(v *Value) bool { } // match: (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWUload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3768,7 +3768,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWUload(v *Value) bool { } v.reset(OpMIPS64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3881,7 +3881,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWload [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3897,7 +3897,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWload(v *Value) bool { } v.reset(OpMIPS64MOVWload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -4045,7 +4045,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWstore [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4062,7 +4062,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWstore(v *Value) bool { } v.reset(OpMIPS64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -4144,7 +4144,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWstorezero(v *Value) bool { } // match: (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWstorezero [off1+int32(off2)] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -4160,7 +4160,7 @@ func rewriteValueMIPS64_OpMIPS64MOVWstorezero(v *Value) bool { } v.reset(OpMIPS64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go index e5a23e8625..7d4cf73fd8 100644 --- a/src/cmd/compile/internal/ssa/rewritePPC64.go +++ b/src/cmd/compile/internal/ssa/rewritePPC64.go @@ -5430,7 +5430,7 @@ func rewriteValuePPC64_OpPPC64FMOVDload(v *Value) bool { } // match: (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5447,7 +5447,7 @@ func rewriteValuePPC64_OpPPC64FMOVDload(v *Value) bool { } v.reset(OpPPC64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5519,7 +5519,7 @@ func rewriteValuePPC64_OpPPC64FMOVDstore(v *Value) bool { } // match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5537,7 +5537,7 @@ func rewriteValuePPC64_OpPPC64FMOVDstore(v *Value) bool { } v.reset(OpPPC64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -5548,7 +5548,7 @@ func rewriteValuePPC64_OpPPC64FMOVSload(v *Value) bool { v_0 := v.Args[0] // match: (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5565,7 +5565,7 @@ func rewriteValuePPC64_OpPPC64FMOVSload(v *Value) bool { } v.reset(OpPPC64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -5620,7 +5620,7 @@ func rewriteValuePPC64_OpPPC64FMOVSstore(v *Value) bool { } // match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -5638,7 +5638,7 @@ func rewriteValuePPC64_OpPPC64FMOVSstore(v *Value) bool { } v.reset(OpPPC64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -6606,7 +6606,7 @@ func rewriteValuePPC64_OpPPC64MOVBZload(v *Value) bool { v_0 := v.Args[0] // match: (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVBZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -6623,7 +6623,7 @@ func rewriteValuePPC64_OpPPC64MOVBZload(v *Value) bool { } v.reset(OpPPC64MOVBZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -7358,7 +7358,7 @@ func rewriteValuePPC64_OpPPC64MOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7376,7 +7376,7 @@ func rewriteValuePPC64_OpPPC64MOVBstore(v *Value) bool { } v.reset(OpPPC64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -8331,7 +8331,7 @@ func rewriteValuePPC64_OpPPC64MOVBstorezero(v *Value) bool { } // match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) - // result: (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8348,7 +8348,7 @@ func rewriteValuePPC64_OpPPC64MOVBstorezero(v *Value) bool { } v.reset(OpPPC64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, mem) return true } @@ -8376,7 +8376,7 @@ func rewriteValuePPC64_OpPPC64MOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8393,7 +8393,7 @@ func rewriteValuePPC64_OpPPC64MOVDload(v *Value) bool { } v.reset(OpPPC64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -8529,7 +8529,7 @@ func rewriteValuePPC64_OpPPC64MOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8547,7 +8547,7 @@ func rewriteValuePPC64_OpPPC64MOVDstore(v *Value) bool { } v.reset(OpPPC64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -8663,7 +8663,7 @@ func rewriteValuePPC64_OpPPC64MOVDstorezero(v *Value) bool { } // match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 - // result: (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8680,7 +8680,7 @@ func rewriteValuePPC64_OpPPC64MOVDstorezero(v *Value) bool { } v.reset(OpPPC64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, mem) return true } @@ -8757,7 +8757,7 @@ func rewriteValuePPC64_OpPPC64MOVHZload(v *Value) bool { v_0 := v.Args[0] // match: (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVHZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8774,7 +8774,7 @@ func rewriteValuePPC64_OpPPC64MOVHZload(v *Value) bool { } v.reset(OpPPC64MOVHZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9279,7 +9279,7 @@ func rewriteValuePPC64_OpPPC64MOVHload(v *Value) bool { v_0 := v.Args[0] // match: (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9296,7 +9296,7 @@ func rewriteValuePPC64_OpPPC64MOVHload(v *Value) bool { } v.reset(OpPPC64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9673,7 +9673,7 @@ func rewriteValuePPC64_OpPPC64MOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9691,7 +9691,7 @@ func rewriteValuePPC64_OpPPC64MOVHstore(v *Value) bool { } v.reset(OpPPC64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -9989,7 +9989,7 @@ func rewriteValuePPC64_OpPPC64MOVHstorezero(v *Value) bool { } // match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) - // result: (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10006,7 +10006,7 @@ func rewriteValuePPC64_OpPPC64MOVHstorezero(v *Value) bool { } v.reset(OpPPC64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, mem) return true } @@ -10053,7 +10053,7 @@ func rewriteValuePPC64_OpPPC64MOVWZload(v *Value) bool { v_0 := v.Args[0] // match: (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVWZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10070,7 +10070,7 @@ func rewriteValuePPC64_OpPPC64MOVWZload(v *Value) bool { } v.reset(OpPPC64MOVWZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -10582,7 +10582,7 @@ func rewriteValuePPC64_OpPPC64MOVWload(v *Value) bool { v_0 := v.Args[0] // match: (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10599,7 +10599,7 @@ func rewriteValuePPC64_OpPPC64MOVWload(v *Value) bool { } v.reset(OpPPC64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -10995,7 +10995,7 @@ func rewriteValuePPC64_OpPPC64MOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11013,7 +11013,7 @@ func rewriteValuePPC64_OpPPC64MOVWstore(v *Value) bool { } v.reset(OpPPC64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } @@ -11191,7 +11191,7 @@ func rewriteValuePPC64_OpPPC64MOVWstorezero(v *Value) bool { } // match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) - // result: (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem) + // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11208,7 +11208,7 @@ func rewriteValuePPC64_OpPPC64MOVWstorezero(v *Value) bool { } v.reset(OpPPC64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteRISCV64.go b/src/cmd/compile/internal/ssa/rewriteRISCV64.go index c337ffbfe7..67d3ecf2cc 100644 --- a/src/cmd/compile/internal/ssa/rewriteRISCV64.go +++ b/src/cmd/compile/internal/ssa/rewriteRISCV64.go @@ -2466,7 +2466,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBUload(v *Value) bool { v_0 := v.Args[0] // match: (MOVBUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2482,7 +2482,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBUload(v *Value) bool { } v.reset(OpRISCV64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -2565,7 +2565,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBload(v *Value) bool { v_0 := v.Args[0] // match: (MOVBload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2581,7 +2581,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBload(v *Value) bool { } v.reset(OpRISCV64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -2665,7 +2665,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBstore(v *Value) bool { v_0 := v.Args[0] // match: (MOVBstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2682,7 +2682,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBstore(v *Value) bool { } v.reset(OpRISCV64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -2833,7 +2833,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBstorezero(v *Value) bool { v_0 := v.Args[0] // match: (MOVBstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2849,7 +2849,7 @@ func rewriteValueRISCV64_OpRISCV64MOVBstorezero(v *Value) bool { } v.reset(OpRISCV64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -2926,7 +2926,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDload(v *Value) bool { v_0 := v.Args[0] // match: (MOVDload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -2942,7 +2942,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDload(v *Value) bool { } v.reset(OpRISCV64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -2991,7 +2991,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDstore(v *Value) bool { v_0 := v.Args[0] // match: (MOVDstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3008,7 +3008,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDstore(v *Value) bool { } v.reset(OpRISCV64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3057,7 +3057,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDstorezero(v *Value) bool { v_0 := v.Args[0] // match: (MOVDstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3073,7 +3073,7 @@ func rewriteValueRISCV64_OpRISCV64MOVDstorezero(v *Value) bool { } v.reset(OpRISCV64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3105,7 +3105,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHUload(v *Value) bool { v_0 := v.Args[0] // match: (MOVHUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3121,7 +3121,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHUload(v *Value) bool { } v.reset(OpRISCV64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3226,7 +3226,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHload(v *Value) bool { v_0 := v.Args[0] // match: (MOVHload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3242,7 +3242,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHload(v *Value) bool { } v.reset(OpRISCV64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3370,7 +3370,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHstore(v *Value) bool { v_0 := v.Args[0] // match: (MOVHstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3387,7 +3387,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHstore(v *Value) bool { } v.reset(OpRISCV64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3504,7 +3504,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHstorezero(v *Value) bool { v_0 := v.Args[0] // match: (MOVHstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3520,7 +3520,7 @@ func rewriteValueRISCV64_OpRISCV64MOVHstorezero(v *Value) bool { } v.reset(OpRISCV64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -3552,7 +3552,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWUload(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWUload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3568,7 +3568,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWUload(v *Value) bool { } v.reset(OpRISCV64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3695,7 +3695,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWload(v *Value) bool { v_0 := v.Args[0] // match: (MOVWload [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3711,7 +3711,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWload(v *Value) bool { } v.reset(OpRISCV64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -3872,7 +3872,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWstore(v *Value) bool { v_0 := v.Args[0] // match: (MOVWstore [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3889,7 +3889,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWstore(v *Value) bool { } v.reset(OpRISCV64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -3972,7 +3972,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWstorezero(v *Value) bool { v_0 := v.Args[0] // match: (MOVWstorezero [off1] {sym1} (MOVaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) - // result: (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem) + // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -3988,7 +3988,7 @@ func rewriteValueRISCV64_OpRISCV64MOVWstorezero(v *Value) bool { } v.reset(OpRISCV64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } diff --git a/src/cmd/compile/internal/ssa/rewriteS390X.go b/src/cmd/compile/internal/ssa/rewriteS390X.go index 35b691c12d..8c3c61d584 100644 --- a/src/cmd/compile/internal/ssa/rewriteS390X.go +++ b/src/cmd/compile/internal/ssa/rewriteS390X.go @@ -5635,7 +5635,7 @@ func rewriteValueS390X_OpS390XADDWload(v *Value) bool { } // match: (ADDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ADDWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ADDWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -5652,7 +5652,7 @@ func rewriteValueS390X_OpS390XADDWload(v *Value) bool { } v.reset(OpS390XADDWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -5815,7 +5815,7 @@ func rewriteValueS390X_OpS390XADDload(v *Value) bool { } // match: (ADDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ADDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ADDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -5832,7 +5832,7 @@ func rewriteValueS390X_OpS390XADDload(v *Value) bool { } v.reset(OpS390XADDload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -6191,7 +6191,7 @@ func rewriteValueS390X_OpS390XANDWload(v *Value) bool { } // match: (ANDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ANDWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ANDWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -6208,7 +6208,7 @@ func rewriteValueS390X_OpS390XANDWload(v *Value) bool { } v.reset(OpS390XANDWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -6316,7 +6316,7 @@ func rewriteValueS390X_OpS390XANDload(v *Value) bool { } // match: (ANDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ANDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ANDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -6333,7 +6333,7 @@ func rewriteValueS390X_OpS390XANDload(v *Value) bool { } v.reset(OpS390XANDload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -7439,7 +7439,7 @@ func rewriteValueS390X_OpS390XFMOVDload(v *Value) bool { } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7455,7 +7455,7 @@ func rewriteValueS390X_OpS390XFMOVDload(v *Value) bool { } v.reset(OpS390XFMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -7489,7 +7489,7 @@ func rewriteValueS390X_OpS390XFMOVDstore(v *Value) bool { } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7506,7 +7506,7 @@ func rewriteValueS390X_OpS390XFMOVDstore(v *Value) bool { } v.reset(OpS390XFMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -7556,7 +7556,7 @@ func rewriteValueS390X_OpS390XFMOVSload(v *Value) bool { } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7572,7 +7572,7 @@ func rewriteValueS390X_OpS390XFMOVSload(v *Value) bool { } v.reset(OpS390XFMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -7606,7 +7606,7 @@ func rewriteValueS390X_OpS390XFMOVSstore(v *Value) bool { } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -7623,7 +7623,7 @@ func rewriteValueS390X_OpS390XFMOVSstore(v *Value) bool { } v.reset(OpS390XFMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8101,7 +8101,7 @@ func rewriteValueS390X_OpS390XMOVBZload(v *Value) bool { } // match: (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8117,7 +8117,7 @@ func rewriteValueS390X_OpS390XMOVBZload(v *Value) bool { } v.reset(OpS390XMOVBZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -8371,7 +8371,7 @@ func rewriteValueS390X_OpS390XMOVBload(v *Value) bool { } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8387,7 +8387,7 @@ func rewriteValueS390X_OpS390XMOVBload(v *Value) bool { } v.reset(OpS390XMOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -8658,7 +8658,7 @@ func rewriteValueS390X_OpS390XMOVBstore(v *Value) bool { } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8675,7 +8675,7 @@ func rewriteValueS390X_OpS390XMOVBstore(v *Value) bool { } v.reset(OpS390XMOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -8931,7 +8931,7 @@ func rewriteValueS390X_OpS390XMOVBstoreconst(v *Value) bool { } // match: (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) // cond: ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVBstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -8947,7 +8947,7 @@ func rewriteValueS390X_OpS390XMOVBstoreconst(v *Value) bool { } v.reset(OpS390XMOVBstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9025,7 +9025,7 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value) bool { } // match: (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (MOVDaddridx [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9041,13 +9041,13 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value) bool { } v.reset(OpS390XMOVDaddridx) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && y.Op != OpSB - // result: (MOVDaddridx [off1+off2] {mergeSymTyped(sym1,sym2)} x y) + // result: (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9063,7 +9063,7 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value) bool { } v.reset(OpS390XMOVDaddridx) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } @@ -9132,7 +9132,7 @@ func rewriteValueS390X_OpS390XMOVDload(v *Value) bool { } // match: (MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%8 == 0 && (off1+off2)%8 == 0)) - // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9149,7 +9149,7 @@ func rewriteValueS390X_OpS390XMOVDload(v *Value) bool { } v.reset(OpS390XMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -9204,7 +9204,7 @@ func rewriteValueS390X_OpS390XMOVDstore(v *Value) bool { } // match: (MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%8 == 0 && (off1+off2)%8 == 0)) - // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9222,7 +9222,7 @@ func rewriteValueS390X_OpS390XMOVDstore(v *Value) bool { } v.reset(OpS390XMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -9335,7 +9335,7 @@ func rewriteValueS390X_OpS390XMOVDstoreconst(v *Value) bool { } // match: (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) // cond: ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVDstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVDstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9351,7 +9351,7 @@ func rewriteValueS390X_OpS390XMOVDstoreconst(v *Value) bool { } v.reset(OpS390XMOVDstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -9518,7 +9518,7 @@ func rewriteValueS390X_OpS390XMOVHZload(v *Value) bool { } // match: (MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) - // result: (MOVHZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9535,7 +9535,7 @@ func rewriteValueS390X_OpS390XMOVHZload(v *Value) bool { } v.reset(OpS390XMOVHZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -9759,7 +9759,7 @@ func rewriteValueS390X_OpS390XMOVHload(v *Value) bool { } // match: (MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) - // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -9776,7 +9776,7 @@ func rewriteValueS390X_OpS390XMOVHload(v *Value) bool { } v.reset(OpS390XMOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -10053,7 +10053,7 @@ func rewriteValueS390X_OpS390XMOVHstore(v *Value) bool { } // match: (MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%2 == 0 && (off1+off2)%2 == 0)) - // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10071,7 +10071,7 @@ func rewriteValueS390X_OpS390XMOVHstore(v *Value) bool { } v.reset(OpS390XMOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -10219,7 +10219,7 @@ func rewriteValueS390X_OpS390XMOVHstoreconst(v *Value) bool { } // match: (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) // cond: ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVHstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVHstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10235,7 +10235,7 @@ func rewriteValueS390X_OpS390XMOVHstoreconst(v *Value) bool { } v.reset(OpS390XMOVHstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -10374,7 +10374,7 @@ func rewriteValueS390X_OpS390XMOVWZload(v *Value) bool { } // match: (MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) - // result: (MOVWZload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10391,7 +10391,7 @@ func rewriteValueS390X_OpS390XMOVWZload(v *Value) bool { } v.reset(OpS390XMOVWZload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -10594,7 +10594,7 @@ func rewriteValueS390X_OpS390XMOVWload(v *Value) bool { } // match: (MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) - // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} base mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10611,7 +10611,7 @@ func rewriteValueS390X_OpS390XMOVWload(v *Value) bool { } v.reset(OpS390XMOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } @@ -10874,7 +10874,7 @@ func rewriteValueS390X_OpS390XMOVWstore(v *Value) bool { } // match: (MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.Elem().Alignment()%4 == 0 && (off1+off2)%4 == 0)) - // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} base val mem) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -10892,7 +10892,7 @@ func rewriteValueS390X_OpS390XMOVWstore(v *Value) bool { } v.reset(OpS390XMOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } @@ -11063,7 +11063,7 @@ func rewriteValueS390X_OpS390XMOVWstoreconst(v *Value) bool { } // match: (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) // cond: ptr.Op != OpSB && canMergeSym(sym1, sym2) && sc.canAdd32(off) - // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSymTyped(sym1, sym2)} ptr mem) + // result: (MOVWstoreconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -11079,7 +11079,7 @@ func rewriteValueS390X_OpS390XMOVWstoreconst(v *Value) bool { } v.reset(OpS390XMOVWstoreconst) v.AuxInt = valAndOffToAuxInt(sc.addOffset32(off)) - v.Aux = symToAux(mergeSymTyped(sym1, sym2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } @@ -11293,7 +11293,7 @@ func rewriteValueS390X_OpS390XMULLDload(v *Value) bool { } // match: (MULLDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (MULLDload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (MULLDload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -11310,7 +11310,7 @@ func rewriteValueS390X_OpS390XMULLDload(v *Value) bool { } v.reset(OpS390XMULLDload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -11496,7 +11496,7 @@ func rewriteValueS390X_OpS390XMULLWload(v *Value) bool { } // match: (MULLWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (MULLWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (MULLWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -11513,7 +11513,7 @@ func rewriteValueS390X_OpS390XMULLWload(v *Value) bool { } v.reset(OpS390XMULLWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -12846,7 +12846,7 @@ func rewriteValueS390X_OpS390XORWload(v *Value) bool { } // match: (ORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ORWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ORWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -12863,7 +12863,7 @@ func rewriteValueS390X_OpS390XORWload(v *Value) bool { } v.reset(OpS390XORWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -12957,7 +12957,7 @@ func rewriteValueS390X_OpS390XORload(v *Value) bool { } // match: (ORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (ORload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (ORload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -12974,7 +12974,7 @@ func rewriteValueS390X_OpS390XORload(v *Value) bool { } v.reset(OpS390XORload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -14333,7 +14333,7 @@ func rewriteValueS390X_OpS390XSUBWload(v *Value) bool { } // match: (SUBWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (SUBWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (SUBWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -14350,7 +14350,7 @@ func rewriteValueS390X_OpS390XSUBWload(v *Value) bool { } v.reset(OpS390XSUBWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -14466,7 +14466,7 @@ func rewriteValueS390X_OpS390XSUBload(v *Value) bool { } // match: (SUBload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (SUBload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (SUBload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -14483,7 +14483,7 @@ func rewriteValueS390X_OpS390XSUBload(v *Value) bool { } v.reset(OpS390XSUBload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -14812,7 +14812,7 @@ func rewriteValueS390X_OpS390XXORWload(v *Value) bool { } // match: (XORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (XORWload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (XORWload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -14829,7 +14829,7 @@ func rewriteValueS390X_OpS390XXORWload(v *Value) bool { } v.reset(OpS390XXORWload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } @@ -14913,7 +14913,7 @@ func rewriteValueS390X_OpS390XXORload(v *Value) bool { } // match: (XORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem) // cond: ptr.Op != OpSB && is20Bit(int64(o1)+int64(o2)) && canMergeSym(s1, s2) - // result: (XORload [o1+o2] {mergeSymTyped(s1, s2)} x ptr mem) + // result: (XORload [o1+o2] {mergeSym(s1, s2)} x ptr mem) for { o1 := auxIntToInt32(v.AuxInt) s1 := auxToSym(v.Aux) @@ -14930,7 +14930,7 @@ func rewriteValueS390X_OpS390XXORload(v *Value) bool { } v.reset(OpS390XXORload) v.AuxInt = int32ToAuxInt(o1 + o2) - v.Aux = symToAux(mergeSymTyped(s1, s2)) + v.Aux = symToAux(mergeSym(s1, s2)) v.AddArg3(x, ptr, mem) return true } |