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path: root/src/cmd/internal/obj/ppc64/asm9.go
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Diffstat (limited to 'src/cmd/internal/obj/ppc64/asm9.go')
-rw-r--r--src/cmd/internal/obj/ppc64/asm9.go178
1 files changed, 128 insertions, 50 deletions
diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go
index 98b453de6c..9f06bdf8b3 100644
--- a/src/cmd/internal/obj/ppc64/asm9.go
+++ b/src/cmd/internal/obj/ppc64/asm9.go
@@ -160,6 +160,8 @@ var optab = []Optab{
{ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0},
{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0},
+ {AEXTSWSLI, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0},
+ {AEXTSWSLI, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0},
{ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0},
{ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0},
{ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
@@ -1877,6 +1879,9 @@ func buildop(ctxt *obj.Link) {
case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
opset(ASRAWCC, r0)
+ case AEXTSWSLI:
+ opset(AEXTSWSLICC, r0)
+
case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
opset(ASRADCC, r0)
@@ -1904,6 +1909,7 @@ func buildop(ctxt *obj.Link) {
opset(ARLWMICC, r0)
opset(ARLWNM, r0)
opset(ARLWNMCC, r0)
+ opset(ACLRLSLWI, r0)
case ARLDMI:
opset(ARLDMICC, r0)
@@ -1922,6 +1928,9 @@ func buildop(ctxt *obj.Link) {
opset(ARLDICLCC, r0)
opset(ARLDICR, r0)
opset(ARLDICRCC, r0)
+ opset(ARLDIC, r0)
+ opset(ARLDICCC, r0)
+ opset(ACLRLSLDI, r0)
case AFMOVD:
opset(AFMOVDCC, r0)
@@ -2185,49 +2194,54 @@ func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
}
+func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
+ return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
+}
+
func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
}
const (
/* each rhs is OPVCC(_, _, _, _) */
- OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
- OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
- OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
- OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
- OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
- OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
- OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
- OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
- OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
- OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
- OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
- OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
- OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
- OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0
- OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
- OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
- OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
- OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
- OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
- OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
- OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0
- OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0
- OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
- OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
- OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
- OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
- OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
- OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
- OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
- OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
- OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
- OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
- OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
- OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
- OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
- OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
- OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
+ OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
+ OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
+ OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
+ OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
+ OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
+ OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
+ OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
+ OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
+ OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
+ OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
+ OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
+ OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
+ OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
+ OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0
+ OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
+ OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
+ OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
+ OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
+ OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
+ OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
+ OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0
+ OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0
+ OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
+ OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
+ OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
+ OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
+ OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
+ OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
+ OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
+ OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
+ OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
+ OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
+ OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
+ OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
+ OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
+ OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
+ OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
+ OP_EXTSWSLI = 31<<26 | 445<<2
)
func oclass(a *obj.Addr) int {
@@ -2734,13 +2748,31 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
case ARLDICR, ARLDICRCC:
me := int(d)
sh := c.regoff(&p.From)
+ if me < 0 || me > 63 || sh > 63 {
+ c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh)
+ }
o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me))
- case ARLDICL, ARLDICLCC:
+ case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
mb := int(d)
sh := c.regoff(&p.From)
+ if mb < 0 || mb > 63 || sh > 63 {
+ c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh)
+ }
o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb))
+ case ACLRLSLDI:
+ // This is an extended mnemonic defined in the ISA section C.8.1
+ // clrlsldi ra,rs,n,b --> rldic ra,rs,n,b-n
+ // It maps onto RLDIC so is directly generated here based on the operands from
+ // the clrlsldi.
+ b := int(d)
+ n := c.regoff(&p.From)
+ if n > int32(b) || b > 63 {
+ c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b)
+ }
+ o1 = AOP_RLDIC(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
+
default:
c.ctxt.Diag("unexpected op in rldc case\n%v", p)
a = 0
@@ -2943,14 +2975,21 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
case AROTL:
a = int(0)
op = OP_RLDICL
+ case AEXTSWSLI:
+ a = int(v)
default:
c.ctxt.Diag("unexpected op in sldi case\n%v", p)
a = 0
o1 = 0
}
- o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
- if p.As == ASLDCC || p.As == ASRDCC {
+ if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
+ o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
+
+ } else {
+ o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
+ }
+ if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
o1 |= 1 // Set the condition code bit
}
@@ -3354,18 +3393,43 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
case 62: /* rlwmi $sh,s,$mask,a */
v := c.regoff(&p.From)
-
- var mask [2]uint8
- c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
- o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
- o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
+ switch p.As {
+ case ACLRLSLWI:
+ b := c.regoff(p.GetFrom3())
+ // This is an extended mnemonic described in the ISA C.8.2
+ // clrlslwi ra,rs,n,b -> rlwinm ra,rs,n,b-n,31-n
+ // It maps onto rlwinm which is directly generated here.
+ if v < 0 || v > 32 || b > 32 {
+ c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, b)
+ }
+ o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(v), uint32(b-v), uint32(31-v))
+ default:
+ var mask [2]uint8
+ c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
+ o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
+ o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
+ }
case 63: /* rlwmi b,s,$mask,a */
- var mask [2]uint8
- c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
-
- o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg))
- o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
+ v := c.regoff(&p.From)
+ switch p.As {
+ case ACLRLSLWI:
+ b := c.regoff(p.GetFrom3())
+ if v > b || b > 32 {
+ // Message will match operands from the ISA even though in the
+ // code it uses 'v'
+ c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, b)
+ }
+ // This is an extended mnemonic described in the ISA C.8.2
+ // clrlslwi ra,rs,n,b -> rlwinm ra,rs,n,b-n,31-n
+ // It generates the rlwinm directly here.
+ o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(v), uint32(b-v), uint32(31-v))
+ default:
+ var mask [2]uint8
+ c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
+ o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
+ o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
+ }
case 64: /* mtfsf fr[, $m] {,fpcsr} */
var v int32
@@ -4277,6 +4341,11 @@ func (c *ctxt9) oprrr(a obj.As) uint32 {
case ARLDICRCC:
return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr.
+ case ARLDIC:
+ return OPVCC(30, 0, 0, 0) | 4<<1 // rldic
+ case ARLDICCC:
+ return OPVCC(30, 0, 0, 1) | 4<<1 // rldic.
+
case ASYSCALL:
return OPVCC(17, 1, 0, 0)
@@ -4298,6 +4367,11 @@ func (c *ctxt9) oprrr(a obj.As) uint32 {
case ASRADCC:
return OPVCC(31, 794, 0, 1)
+ case AEXTSWSLI:
+ return OPVCC(31, 445, 0, 0)
+ case AEXTSWSLICC:
+ return OPVCC(31, 445, 0, 1)
+
case ASRW:
return OPVCC(31, 536, 0, 0)
case ASRWCC:
@@ -4961,6 +5035,10 @@ func (c *ctxt9) opirr(a obj.As) uint32 {
return OPVCC(31, (413 << 1), 0, 0)
case ASRADCC:
return OPVCC(31, (413 << 1), 0, 1)
+ case AEXTSWSLI:
+ return OPVCC(31, 445, 0, 0)
+ case AEXTSWSLICC:
+ return OPVCC(31, 445, 0, 1)
case ASTSW:
return OPVCC(31, 725, 0, 0)
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