diff options
Diffstat (limited to 'src/cmd/compile/internal/riscv64/ssa.go')
| -rw-r--r-- | src/cmd/compile/internal/riscv64/ssa.go | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go index 70c29a4b7b..5576dd4e48 100644 --- a/src/cmd/compile/internal/riscv64/ssa.go +++ b/src/cmd/compile/internal/riscv64/ssa.go @@ -211,9 +211,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Type = obj.TYPE_REG p.To.Reg = rd case ssa.OpRISCV64MOVDnop: - if v.Reg() != v.Args[0].Reg() { - v.Fatalf("input[0] and output not in same register %s", v.LongString()) - } // nothing to do case ssa.OpLoadReg: if v.Type.IsFlags() { @@ -513,6 +510,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p6 := s.Prog(obj.ANOP) p2.To.SetTarget(p6) + case ssa.OpRISCV64LoweredAtomicAnd32, ssa.OpRISCV64LoweredAtomicOr32: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[1].Reg() + p.To.Type = obj.TYPE_MEM + p.To.Reg = v.Args[0].Reg() + p.RegTo2 = riscv.REG_ZERO + case ssa.OpRISCV64LoweredZero: mov, sz := largestMove(v.AuxInt) |