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author | Alejandro GarcĂa Montoro <alejandro.garciamontoro@gmail.com> | 2020-12-30 18:41:36 +0100 |
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committer | Josh Bleecher Snyder <josharian@gmail.com> | 2021-02-24 19:25:49 +0000 |
commit | bf48163e8f2b604f3b9e83951e331cd11edd8495 (patch) | |
tree | f331bc8eb53e8fd69fb722384958cbff86695ab0 /test/codegen | |
parent | b7f62daa59ea5983d5825e166abc527d4ea69777 (diff) | |
download | go-bf48163e8f2b604f3b9e83951e331cd11edd8495.tar.gz go-bf48163e8f2b604f3b9e83951e331cd11edd8495.zip |
cmd/compile: add rule to coalesce writes
The code generated when storing eight bytes loaded from memory created a
series of small writes instead of a single, large one. The specific
pattern of instructions generated stored 1 byte, then 2 bytes, then 4
bytes, and finally 1 byte.
The new rules match this specific pattern both for amd64 and for s390x,
and convert it into a single instruction to store the 8 bytes. arm64 and
ppc64le already generated the right code, but the new codegen test
covers also those architectures.
Fixes #41663
Change-Id: Ifb9b464be2d59c2ed5034acf7b9c3e473f344030
Reviewed-on: https://go-review.googlesource.com/c/go/+/280456
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
Trust: Josh Bleecher Snyder <josharian@gmail.com>
Trust: Jason A. Donenfeld <Jason@zx2c4.com>
Run-TryBot: Josh Bleecher Snyder <josharian@gmail.com>
TryBot-Result: Go Bot <gobot@golang.org>
Diffstat (limited to 'test/codegen')
-rw-r--r-- | test/codegen/memcombine.go | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/test/codegen/memcombine.go b/test/codegen/memcombine.go index 6ad9514557..121f394f29 100644 --- a/test/codegen/memcombine.go +++ b/test/codegen/memcombine.go @@ -367,6 +367,15 @@ func store_le64_idx(b []byte, idx int) { binary.LittleEndian.PutUint64(b[idx:], sink64) } +func store_le64_load(b []byte, x *[8]byte) { + _ = b[8] + // amd64:-`MOV[BWL]` + // arm64:-`MOV[BWH]` + // ppc64le:-`MOV[BWH]` + // s390x:-`MOVB`,-`MOV[WH]BR` + binary.LittleEndian.PutUint64(b, binary.LittleEndian.Uint64(x[:])) +} + func store_le32(b []byte) { // amd64:`MOVL\s` // arm64:`MOVW`,-`MOV[BH]` |