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authorCherry Mui <cherryyz@google.com>2022-01-18 18:36:00 -0500
committerCherry Mui <cherryyz@google.com>2022-02-07 17:28:28 +0000
commit1651426f77a19cca90c4f3be4dcd10d33da9e7ea (patch)
treef7b05f45dba2b8ce1621f4d107c1d0ffd753c814 /src
parent17e179e187861a7a095d7ae85ddcfc94804d7d6b (diff)
downloadgo-1651426f77a19cca90c4f3be4dcd10d33da9e7ea.tar.gz
go-1651426f77a19cca90c4f3be4dcd10d33da9e7ea.zip
[release-branch.go1.17] cmd/compile: don't elide extension for LoadReg to FP register on MIPS64
For an extension operation like MOVWreg, if the operand is already extended, we optimize the second extension out. Usually a LoadReg of a proper type would come already extended, as a MOVW/MOVWU etc. instruction does. But for a LoadReg to a floating point register, the instruction does not do the extension. So we cannot elide the extension. Updates #50671. Fixes #50683. Change-Id: Id8991df78d5acdecd3fd6138c558428cbd5f6ba3 Reviewed-on: https://go-review.googlesource.com/c/go/+/379236 Trust: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com> (cherry picked from commit d93ff73ae207763871bee38590242be968b2e743) Reviewed-on: https://go-review.googlesource.com/c/go/+/379514
Diffstat (limited to 'src')
-rw-r--r--src/cmd/compile/internal/mips64/ssa.go5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cmd/compile/internal/mips64/ssa.go b/src/cmd/compile/internal/mips64/ssa.go
index e821a00876..5cf05445cc 100644
--- a/src/cmd/compile/internal/mips64/ssa.go
+++ b/src/cmd/compile/internal/mips64/ssa.go
@@ -320,7 +320,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
for a.Op == ssa.OpCopy || a.Op == ssa.OpMIPS64MOVVreg {
a = a.Args[0]
}
- if a.Op == ssa.OpLoadReg {
+ if a.Op == ssa.OpLoadReg && mips.REG_R0 <= a.Reg() && a.Reg() <= mips.REG_R31 {
+ // LoadReg from a narrower type does an extension, except loading
+ // to a floating point register. So only eliminate the extension
+ // if it is loaded to an integer register.
t := a.Type
switch {
case v.Op == ssa.OpMIPS64MOVBreg && t.Size() == 1 && t.IsSigned(),