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author | Cherry Zhang <cherryyz@google.com> | 2016-12-03 19:17:16 -0500 |
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committer | Cherry Zhang <cherryyz@google.com> | 2016-12-05 03:53:56 +0000 |
commit | ed0b232cdc48398c2074369852e5db8bdcb866aa (patch) | |
tree | d20e6c8576911b4985cfbf5945ed59aee3b865d9 /src/cmd/compile/internal/ssa/writebarrier_test.go | |
parent | af67f7de3f7b0d26f95d813022f876eef1fa3889 (diff) | |
download | go-ed0b232cdc48398c2074369852e5db8bdcb866aa.tar.gz go-ed0b232cdc48398c2074369852e5db8bdcb866aa.zip |
cmd/compile: find last StoreWB explicitly
In writebarrier phase, a chain of StoreWBs is rewritten to branchy
code to invoke write barriers, and the last store in the chain is
spliced into a Phi op to join the memory of the two branches. We
must find the last store explicitly, since the values are not
scheduled and they may not come in dependency order.
Fixes #18169.
Change-Id: If547e3c562ef0669bc5622c1bb711904dc36314d
Reviewed-on: https://go-review.googlesource.com/33915
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
Diffstat (limited to 'src/cmd/compile/internal/ssa/writebarrier_test.go')
-rw-r--r-- | src/cmd/compile/internal/ssa/writebarrier_test.go | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/ssa/writebarrier_test.go b/src/cmd/compile/internal/ssa/writebarrier_test.go new file mode 100644 index 0000000000..c2ba695971 --- /dev/null +++ b/src/cmd/compile/internal/ssa/writebarrier_test.go @@ -0,0 +1,29 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestWriteBarrierStoreOrder(t *testing.T) { + // Make sure writebarrier phase works even StoreWB ops are not in dependency order + c := testConfig(t) + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Valu("sp", OpSP, TypeInvalid, 0, nil), + Valu("v", OpConstNil, ptrType, 0, nil), + Valu("addr1", OpAddr, ptrType, 0, nil, "sb"), + Valu("wb2", OpStoreWB, TypeMem, 8, nil, "addr1", "v", "wb1"), + Valu("wb1", OpStoreWB, TypeMem, 8, nil, "addr1", "v", "start"), // wb1 and wb2 are out of order + Goto("exit")), + Bloc("exit", + Exit("wb2"))) + + CheckFunc(fun.f) + writebarrier(fun.f) + CheckFunc(fun.f) +} |