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authorJoel Sing <joel@sing.id.au>2020-02-26 04:00:10 +1100
committerJoel Sing <joel@sing.id.au>2020-02-28 14:33:28 +0000
commit8955a56da015890f317d5f6919391503b854d93a (patch)
tree59483143777c46d5d25fe01103dd9f3c1b1ffd0f /src/cmd/compile/internal/ssa/opGen.go
parent44286d09c5fcdb703624fad6ce24306294cab1fe (diff)
downloadgo-8955a56da015890f317d5f6919391503b854d93a.tar.gz
go-8955a56da015890f317d5f6919391503b854d93a.zip
cmd/compile: improve SignExt32to64 on riscv64
SignExt32to64 can be implemented with a single ADDIW instruction, rather than the two shifts that are in use currently. Change-Id: Ie1bbaef4018f1ba5162773fc64fa5a887457cfc9 Reviewed-on: https://go-review.googlesource.com/c/go/+/220922 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/cmd/compile/internal/ssa/opGen.go')
-rw-r--r--src/cmd/compile/internal/ssa/opGen.go15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index a810d9fbc6..b951065e7c 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1884,6 +1884,7 @@ const (
OpRISCV64ADD
OpRISCV64ADDI
+ OpRISCV64ADDIW
OpRISCV64SUB
OpRISCV64SUBW
OpRISCV64MUL
@@ -25016,6 +25017,20 @@ var opcodeTable = [...]opInfo{
},
},
{
+ name: "ADDIW",
+ auxType: auxInt64,
+ argLen: 1,
+ asm: riscv.AADDIW,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
+ },
+ outputs: []outputInfo{
+ {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
+ },
+ },
+ },
+ {
name: "SUB",
argLen: 2,
asm: riscv.ASUB,