diff options
| author | Joel Sing <joel@sing.id.au> | 2020-03-03 03:45:22 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2020-03-15 08:19:07 +0000 |
| commit | 26154f31ad6c801d8bad5ef58df1e9263c6beec7 (patch) | |
| tree | c9dd979940d6dcea886b70bdf41cbe17331c995b /src/cmd/compile/internal/ssa/opGen.go | |
| parent | 7b2f0ba5b91b4b2b659fb46638ff56f51be9b2b5 (diff) | |
| download | go-26154f31ad6c801d8bad5ef58df1e9263c6beec7.tar.gz go-26154f31ad6c801d8bad5ef58df1e9263c6beec7.zip | |
cmd/compile: use NEG/NEGW pseudo-instructions on riscv64
Also rewrite subtraction of zero to NEG/NEGW.
Change-Id: I216e286d1860055f2a07fe2f772cd50f366ea097
Reviewed-on: https://go-review.googlesource.com/c/go/+/221691
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/compile/internal/ssa/opGen.go')
| -rw-r--r-- | src/cmd/compile/internal/ssa/opGen.go | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index 019c76ec0b..481b404bf3 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -1887,6 +1887,8 @@ const ( OpRISCV64ADD OpRISCV64ADDI OpRISCV64ADDIW + OpRISCV64NEG + OpRISCV64NEGW OpRISCV64SUB OpRISCV64SUBW OpRISCV64MUL @@ -25059,6 +25061,32 @@ var opcodeTable = [...]opInfo{ }, }, { + name: "NEG", + argLen: 1, + asm: riscv.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + asm: riscv.ANEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 + }, + }, + }, + { name: "SUB", argLen: 2, asm: riscv.ASUB, |