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| author | Josh Bleecher Snyder <josharian@gmail.com> | 2020-02-24 13:53:53 -0800 |
|---|---|---|
| committer | Josh Bleecher Snyder <josharian@gmail.com> | 2020-02-27 20:34:49 +0000 |
| commit | 2c859eae1da367ab292f65ca4fed4f6c89d644f9 (patch) | |
| tree | 13a259b0ad341540709f06a07ea0205118fa2ef4 /src/cmd/compile/internal/ssa/gen/RISCV64.rules | |
| parent | 4ae1879dda1a20176dddc62e827404c75a869fa0 (diff) | |
| download | go-2c859eae1da367ab292f65ca4fed4f6c89d644f9.tar.gz go-2c859eae1da367ab292f65ca4fed4f6c89d644f9.zip | |
cmd/compile: ignore div/mod in prove on non-x86 architectures
Instead of writing AuxInt during prove and then zeroing it during lower,
just don't write it in the first place.
Passes toolstash-check -all.
Change-Id: Iea4b555029a9d69332e835536f9cf3a42b8223db
Reviewed-on: https://go-review.googlesource.com/c/go/+/220682
Run-TryBot: Josh Bleecher Snyder <josharian@gmail.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/compile/internal/ssa/gen/RISCV64.rules')
| -rw-r--r-- | src/cmd/compile/internal/ssa/gen/RISCV64.rules | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cmd/compile/internal/ssa/gen/RISCV64.rules b/src/cmd/compile/internal/ssa/gen/RISCV64.rules index 316e5f3726..e2ac4ea5e6 100644 --- a/src/cmd/compile/internal/ssa/gen/RISCV64.rules +++ b/src/cmd/compile/internal/ssa/gen/RISCV64.rules @@ -43,9 +43,9 @@ (Div32F ...) -> (FDIVS ...) (Div64F ...) -> (FDIVD ...) -(Div64 [a] x y) -> (DIV x y) +(Div64 ...) -> (DIV ...) (Div64u ...) -> (DIVU ...) -(Div32 [a] x y) -> (DIVW x y) +(Div32 ...) -> (DIVW ...) (Div32u ...) -> (DIVUW ...) (Div16 x y) -> (DIVW (SignExt16to32 x) (SignExt16to32 y)) (Div16u x y) -> (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y)) @@ -60,9 +60,9 @@ // (x + y) / 2 -> (x / 2) + (y / 2) + (x & y & 1) (Avg64u <t> x y) -> (ADD (ADD <t> (SRLI <t> [1] x) (SRLI <t> [1] y)) (ANDI <t> [1] (AND <t> x y))) -(Mod64 [a] x y) -> (REM x y) +(Mod64 ...) -> (REM ...) (Mod64u ...) -> (REMU ...) -(Mod32 [a] x y) -> (REMW x y) +(Mod32 ...) -> (REMW ...) (Mod32u ...) -> (REMUW ...) (Mod16 x y) -> (REMW (SignExt16to32 x) (SignExt16to32 y)) (Mod16u x y) -> (REMUW (ZeroExt16to32 x) (ZeroExt16to32 y)) |