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| author | Than McIntosh <thanm@google.com> | 2021-11-04 14:11:57 -0400 |
|---|---|---|
| committer | Than McIntosh <thanm@google.com> | 2021-11-04 14:11:57 -0400 |
| commit | 06a4b2790c5bb6530e0c4f05277b19c187134f49 (patch) | |
| tree | 09017cea1bfb6b6ba6eb191438232c064d55153d /src/cmd/compile/internal/ssa/gen/ARMOps.go | |
| parent | 35d5cd0dcfb9d06064ec37da1621d24676454058 (diff) | |
| parent | 23991f50b34f8707bcfc7761321bb3b0e9dba10e (diff) | |
| download | go-06a4b2790c5bb6530e0c4f05277b19c187134f49.tar.gz go-06a4b2790c5bb6530e0c4f05277b19c187134f49.zip | |
[dev.boringcrypto.go1.16] all: merge go1.16.10 into dev.boringcrypto.go1.16
Change-Id: I164105d3036f0729da3f0b1dfa034f1d1d6a3a27
Diffstat (limited to 'src/cmd/compile/internal/ssa/gen/ARMOps.go')
| -rw-r--r-- | src/cmd/compile/internal/ssa/gen/ARMOps.go | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cmd/compile/internal/ssa/gen/ARMOps.go b/src/cmd/compile/internal/ssa/gen/ARMOps.go index 70c789937a..1a7eefa50a 100644 --- a/src/cmd/compile/internal/ssa/gen/ARMOps.go +++ b/src/cmd/compile/internal/ssa/gen/ARMOps.go @@ -226,14 +226,15 @@ func init() { // shifts {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << arg1, shift amount is mod 256 - {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt + {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, 0 <= auxInt < 32 {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 256 - {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned + {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned, 0 <= auxInt < 32 {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 256 - {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed + {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed, 0 <= auxInt < 32 {name: "SRR", argLength: 2, reg: gp21}, // arg0 right rotate by arg1 bits - {name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits + {name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits, 0 <= auxInt < 32 + // auxInt for all of these satisfy 0 <= auxInt < 32 {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt {name: "ADDshiftRL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, signed shift |