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| author | Keith Randall <khr@golang.org> | 2020-06-15 14:43:02 -0700 |
|---|---|---|
| committer | Keith Randall <khr@golang.org> | 2020-06-18 20:57:49 +0000 |
| commit | 40ef1faabc44ab8ea28a1cf282ecab723ecb0394 (patch) | |
| tree | 1c04bdc4b2eb3226759499dd6867c6771510ba75 /src/cmd/compile/internal/ssa/flags_amd64_test.s | |
| parent | 377c1536f548ae6295699475683db7574bea3d51 (diff) | |
| download | go-40ef1faabc44ab8ea28a1cf282ecab723ecb0394.tar.gz go-40ef1faabc44ab8ea28a1cf282ecab723ecb0394.zip | |
cmd/compile: redo flag constant ops for arm
Encode the flag results in an auxint field instead of having
one opcode per flag state. This helps us handle the new *noov
branches in a unified manner.
This is only for arm, arm64 is in a subsequent CL.
We could extend to other architectures as well, athough it would
only be cleanup, no behavioral change.
Update #39505
Change-Id: Ia46cea596faad540d1496c5915ab1274571543f0
Reviewed-on: https://go-review.googlesource.com/c/go/+/238077
Run-TryBot: Keith Randall <khr@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/compile/internal/ssa/flags_amd64_test.s')
| -rw-r--r-- | src/cmd/compile/internal/ssa/flags_amd64_test.s | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/ssa/flags_amd64_test.s b/src/cmd/compile/internal/ssa/flags_amd64_test.s new file mode 100644 index 0000000000..8bd87019af --- /dev/null +++ b/src/cmd/compile/internal/ssa/flags_amd64_test.s @@ -0,0 +1,31 @@ +// Copyright 2020 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// +build amd64 + +#include "textflag.h" + +TEXT ·asmAddFlags(SB),NOSPLIT,$0-24 + MOVQ x+0(FP), AX + ADDQ y+8(FP), AX + PUSHFQ + POPQ AX + MOVQ AX, ret+16(FP) + RET + +TEXT ·asmSubFlags(SB),NOSPLIT,$0-24 + MOVQ x+0(FP), AX + SUBQ y+8(FP), AX + PUSHFQ + POPQ AX + MOVQ AX, ret+16(FP) + RET + +TEXT ·asmAndFlags(SB),NOSPLIT,$0-24 + MOVQ x+0(FP), AX + ANDQ y+8(FP), AX + PUSHFQ + POPQ AX + MOVQ AX, ret+16(FP) + RET |