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| author | Meng Zhuo <mzh@golangcn.org> | 2021-07-31 10:20:10 +0000 |
|---|---|---|
| committer | Meng Zhuo <mzh@golangcn.org> | 2021-08-17 01:29:37 +0000 |
| commit | 1951afc9193f8e197cb7dfaf6afed70ea02404cb (patch) | |
| tree | aeb457e9d3096d8bbd03bd3d04d183cd05fdbf62 /src/cmd/compile/internal/riscv64 | |
| parent | 2a193337164c8af8cba3d5c4ec0f36413c528bd8 (diff) | |
| download | go-1951afc9193f8e197cb7dfaf6afed70ea02404cb.tar.gz go-1951afc9193f8e197cb7dfaf6afed70ea02404cb.zip | |
cmd/compile: lowered MulUintptr on riscv64
According to RISCV instruction set manual v2.2 Sec 6.1
MULHU followed by MUL will be fused into one multiply by microarchitecture
name old time/op new time/op delta
MulUintptr/small 11.2ns ±24% 9.2ns ± 0% -17.54% (p=0.000 n=10+9)
MulUintptr/large 15.9ns ± 0% 10.9ns ± 0% -31.55% (p=0.000 n=8+8)
Change-Id: I3d152218f83948cbc5c576bda29dc86e9b4206ee
Reviewed-on: https://go-review.googlesource.com/c/go/+/338753
Trust: Meng Zhuo <mzh@golangcn.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
Diffstat (limited to 'src/cmd/compile/internal/riscv64')
| -rw-r--r-- | src/cmd/compile/internal/riscv64/ssa.go | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go index c635d93b71..d3cbb4ec24 100644 --- a/src/cmd/compile/internal/riscv64/ssa.go +++ b/src/cmd/compile/internal/riscv64/ssa.go @@ -297,6 +297,27 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p1.Reg = r0 p1.To.Type = obj.TYPE_REG p1.To.Reg = v.Reg1() + case ssa.OpRISCV64LoweredMuluover: + r0 := v.Args[0].Reg() + r1 := v.Args[1].Reg() + p := s.Prog(riscv.AMULHU) + p.From.Type = obj.TYPE_REG + p.From.Reg = r1 + p.Reg = r0 + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg1() + p1 := s.Prog(riscv.AMUL) + p1.From.Type = obj.TYPE_REG + p1.From.Reg = r1 + p1.Reg = r0 + p1.To.Type = obj.TYPE_REG + p1.To.Reg = v.Reg0() + p2 := s.Prog(riscv.ASNEZ) + p2.From.Type = obj.TYPE_REG + p2.From.Reg = v.Reg1() + p2.To.Type = obj.TYPE_REG + p2.To.Reg = v.Reg1() + case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FNEGS, ssa.OpRISCV64FSQRTD, ssa.OpRISCV64FNEGD, ssa.OpRISCV64FMVSX, ssa.OpRISCV64FMVDX, ssa.OpRISCV64FCVTSW, ssa.OpRISCV64FCVTSL, ssa.OpRISCV64FCVTWS, ssa.OpRISCV64FCVTLS, |