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author | Michael Pratt <mpratt@google.com> | 2020-10-16 17:07:14 -0400 |
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committer | Michael Pratt <mpratt@google.com> | 2020-10-23 15:11:03 +0000 |
commit | e223c6cf073fe1228c54050a43042b9c5721d4f8 (patch) | |
tree | de6ec377e62ff00774df2856676078444118785f /src/cmd/compile/internal/ppc64 | |
parent | cdb19b4dba58c0e3cabde8b728156dfe273707b3 (diff) | |
download | go-e223c6cf073fe1228c54050a43042b9c5721d4f8.tar.gz go-e223c6cf073fe1228c54050a43042b9c5721d4f8.zip |
cmd/compile: intrinsify runtime/internal/atomic.{And,Or} on PPC64
This is a simple case of changing the operand size of the existing 8-bit
And/Or.
I've also updated a few operand descriptions that were out-of-sync with
the implementation.
Change-Id: I95ac4445d08f7958768aec9a233698a2d652a39a
Reviewed-on: https://go-review.googlesource.com/c/go/+/263150
Run-TryBot: Michael Pratt <mpratt@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
Trust: Michael Pratt <mpratt@google.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/compile/internal/ppc64')
-rw-r--r-- | src/cmd/compile/internal/ppc64/ssa.go | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/cmd/compile/internal/ppc64/ssa.go b/src/cmd/compile/internal/ppc64/ssa.go index 1ece4d999f..79f18bfebb 100644 --- a/src/cmd/compile/internal/ppc64/ssa.go +++ b/src/cmd/compile/internal/ppc64/ssa.go @@ -166,34 +166,46 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { p2.To.Reg = v.Reg1() case ssa.OpPPC64LoweredAtomicAnd8, - ssa.OpPPC64LoweredAtomicOr8: + ssa.OpPPC64LoweredAtomicAnd32, + ssa.OpPPC64LoweredAtomicOr8, + ssa.OpPPC64LoweredAtomicOr32: // LWSYNC - // LBAR (Rarg0), Rtmp + // LBAR/LWAR (Rarg0), Rtmp // AND/OR Rarg1, Rtmp - // STBCCC Rtmp, (Rarg0) + // STBCCC/STWCCC Rtmp, (Rarg0) // BNE -3(PC) + ld := ppc64.ALBAR + st := ppc64.ASTBCCC + if v.Op == ssa.OpPPC64LoweredAtomicAnd32 || v.Op == ssa.OpPPC64LoweredAtomicOr32 { + ld = ppc64.ALWAR + st = ppc64.ASTWCCC + } r0 := v.Args[0].Reg() r1 := v.Args[1].Reg() // LWSYNC - Assuming shared data not write-through-required nor // caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b. plwsync := s.Prog(ppc64.ALWSYNC) plwsync.To.Type = obj.TYPE_NONE - p := s.Prog(ppc64.ALBAR) + // LBAR or LWAR + p := s.Prog(ld) p.From.Type = obj.TYPE_MEM p.From.Reg = r0 p.To.Type = obj.TYPE_REG p.To.Reg = ppc64.REGTMP + // AND/OR reg1,out p1 := s.Prog(v.Op.Asm()) p1.From.Type = obj.TYPE_REG p1.From.Reg = r1 p1.To.Type = obj.TYPE_REG p1.To.Reg = ppc64.REGTMP - p2 := s.Prog(ppc64.ASTBCCC) + // STBCCC or STWCCC + p2 := s.Prog(st) p2.From.Type = obj.TYPE_REG p2.From.Reg = ppc64.REGTMP p2.To.Type = obj.TYPE_MEM p2.To.Reg = r0 p2.RegTo2 = ppc64.REGTMP + // BNE retry p3 := s.Prog(ppc64.ABNE) p3.To.Type = obj.TYPE_BRANCH gc.Patch(p3, p) |