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| author | fanzha02 <fannie.zhang@arm.com> | 2021-01-18 14:32:49 +0800 |
|---|---|---|
| committer | fannie zhang <Fannie.Zhang@arm.com> | 2021-03-18 01:46:58 +0000 |
| commit | f5e6d3e879f487066d1a05b8000a7187247558f7 (patch) | |
| tree | fa8fe9da000478f7086b6aaa66d242e5774b1736 /src/cmd/compile/internal/arm64 | |
| parent | 51e4bb236cb8feb8118ed6dd768ddac834dad2ef (diff) | |
| download | go-f5e6d3e879f487066d1a05b8000a7187247558f7.tar.gz go-f5e6d3e879f487066d1a05b8000a7187247558f7.zip | |
cmd/compile: add rewrite rules for conditional instructions on arm64
This CL adds rewrite rules for CSETM, CSINC, CSINV, and CSNEG. By adding
these rules, we can save one instruction.
For example,
func test(cond bool, a int) int {
if cond {
a++
}
return a
}
Before:
MOVD "".a+8(RSP), R0
ADD $1, R0, R1
MOVBU "".cond(RSP), R2
CMPW $0, R2
CSEL NE, R1, R0, R0
After:
MOVBU "".cond(RSP), R0
CMPW $0, R0
MOVD "".a+8(RSP), R0
CSINC EQ, R0, R0, R0
This patch is a copy of CL 285694. Co-authored-by: JunchenLi
<junchen.li@arm.com>
Change-Id: Ic1a79e8b8ece409b533becfcb7950f11e7b76f24
Reviewed-on: https://go-review.googlesource.com/c/go/+/302231
Trust: fannie zhang <Fannie.Zhang@arm.com>
Run-TryBot: fannie zhang <Fannie.Zhang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
Diffstat (limited to 'src/cmd/compile/internal/arm64')
| -rw-r--r-- | src/cmd/compile/internal/arm64/ssa.go | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/arm64/ssa.go b/src/cmd/compile/internal/arm64/ssa.go index 056a6eb62d..3250b49c92 100644 --- a/src/cmd/compile/internal/arm64/ssa.go +++ b/src/cmd/compile/internal/arm64/ssa.go @@ -956,6 +956,20 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.SetFrom3Reg(r1) p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() + case ssa.OpARM64CSINC, ssa.OpARM64CSINV, ssa.OpARM64CSNEG: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg + p.From.Reg = condBits[ssa.Op(v.AuxInt)] + p.Reg = v.Args[0].Reg() + p.SetFrom3Reg(v.Args[1].Reg()) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + case ssa.OpARM64CSETM: + p := s.Prog(arm64.ACSETM) + p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg + p.From.Reg = condBits[ssa.Op(v.AuxInt)] + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() case ssa.OpARM64DUFFZERO: // runtime.duffzero expects start address in R20 p := s.Prog(obj.ADUFFZERO) |