diff options
| author | eric fang <eric.fang@arm.com> | 2021-08-16 07:25:29 +0000 |
|---|---|---|
| committer | eric fang <eric.fang@arm.com> | 2021-08-20 03:25:17 +0000 |
| commit | c92c2c9d625ff3957d1c9313183fd0fe8f26984e (patch) | |
| tree | c1a44756a5361c693a2b3b638cee1298b608bfe8 /src/cmd/asm | |
| parent | 65074a40867d9c42a6b89f96b9eeef5a39234846 (diff) | |
| download | go-c92c2c9d625ff3957d1c9313183fd0fe8f26984e.tar.gz go-c92c2c9d625ff3957d1c9313183fd0fe8f26984e.zip | |
cmd/internal/obj/arm64: disable the pre and post index formats for pseudo registers
When using the FP or SP pseudo-register to load or store, pre-index and post-index formats
are not supported because the RSP and pseudo registers are not allowed to be modified in this
way. This CL deletes the related entries in optab and adds a few test cases.
Change-Id: Ie30d27d0e7b959242f0e6298b950489669d07989
Reviewed-on: https://go-review.googlesource.com/c/go/+/342770
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: eric fang <eric.fang@arm.com>
Trust: Michael Knyszek <mknyszek@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 145074347f..8b12b16680 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -419,4 +419,8 @@ TEXT errors(SB),$0 ADD R1>>2, RSP, R3 // ERROR "illegal combination" ADDS R2<<3, R3, RSP // ERROR "unexpected SP reference" CMP R1<<5, RSP // ERROR "the left shift amount out of range 0 to 4" + MOVD.P y+8(FP), R1 // ERROR "illegal combination" + MOVD.W x-8(SP), R1 // ERROR "illegal combination" + LDP.P x+8(FP), (R0, R1) // ERROR "illegal combination" + LDP.W x+8(SP), (R0, R1) // ERROR "illegal combination" RET |