diff options
| author | Joel Sing <joel@sing.id.au> | 2020-10-27 23:03:11 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2020-10-29 08:00:50 +0000 |
| commit | 8b517983048205932305905bc01a29bd146cb8d6 (patch) | |
| tree | 6d628e5d112259ffd7685e6313dcc4bc81086e41 /src/cmd/asm | |
| parent | ae82ee4016c44e558b002f0c7ffbb40d698d411e (diff) | |
| download | go-8b517983048205932305905bc01a29bd146cb8d6.tar.gz go-8b517983048205932305905bc01a29bd146cb8d6.zip | |
cmd/asm: remove X27 and S11 register names on riscv64
The X27 register (known as S11 via its ABI name) is the g register on riscv64.
Prevent assembly from referring to it by either of these names.
Change-Id: Iba389eb8e44e097c0142c5b3d92e72bcae8a244a
Reviewed-on: https://go-review.googlesource.com/c/go/+/265519
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/arch/arch.go | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go index 2e5d0ff991..a62e55191e 100644 --- a/src/cmd/asm/internal/arch/arch.go +++ b/src/cmd/asm/internal/arch/arch.go @@ -535,6 +535,9 @@ func archRISCV64() *Arch { // Standard register names. for i := riscv.REG_X0; i <= riscv.REG_X31; i++ { + if i == riscv.REG_G { + continue + } name := fmt.Sprintf("X%d", i-riscv.REG_X0) register[name] = int16(i) } @@ -571,7 +574,7 @@ func archRISCV64() *Arch { register["S8"] = riscv.REG_S8 register["S9"] = riscv.REG_S9 register["S10"] = riscv.REG_S10 - register["S11"] = riscv.REG_S11 + // Skip S11 as it is the g register. register["T3"] = riscv.REG_T3 register["T4"] = riscv.REG_T4 register["T5"] = riscv.REG_T5 |