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| author | eric fang <eric.fang@arm.com> | 2020-11-23 10:59:33 +0000 |
|---|---|---|
| committer | eric fang <eric.fang@arm.com> | 2021-03-04 01:26:21 +0000 |
| commit | 79beddc773ecca50c283dde6aad7c80929da0554 (patch) | |
| tree | 83c492dc5a572cceeaffb9c549714f53d46c5f02 /src/cmd/asm | |
| parent | 12bb256cb30a76b540dbbc1cac38d7044facfa29 (diff) | |
| download | go-79beddc773ecca50c283dde6aad7c80929da0554.tar.gz go-79beddc773ecca50c283dde6aad7c80929da0554.zip | |
cmd/asm: add 128-bit FLDPQ and FSTPQ instructions for arm64
This CL adds assembly support for 128-bit FLDPQ and FSTPQ instructions.
This CL also deletes some wrong pre/post-indexed LDP and STP instructions,
such as {ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
because when the offset type is C_UAUTO4K, pre and post don't work.
Change-Id: Ifd901d4440eb06eb9e86c9dd17518749fdf32848
Reviewed-on: https://go-review.googlesource.com/c/go/+/273668
Trust: eric fang <eric.fang@arm.com>
Run-TryBot: eric fang <eric.fang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64.s | 48 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 3 |
2 files changed, 51 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 91e3a0ca0a..1e6cde7a46 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -982,6 +982,54 @@ again: FSTPS (F3, F4), x(SB) FSTPS (F3, F4), x+8(SB) +// FLDPQ/FSTPQ + FLDPQ -4000(R0), (F1, F2) // 1b803ed1610b40ad + FLDPQ -1024(R0), (F1, F2) // 010860ad + FLDPQ (R0), (F1, F2) // 010840ad + FLDPQ 16(R0), (F1, F2) // 018840ad + FLDPQ -16(R0), (F1, F2) // 01887fad + FLDPQ.W 32(R0), (F1, F2) // 0108c1ad + FLDPQ.P 32(R0), (F1, F2) // 0108c1ac + FLDPQ 11(R0), (F1, F2) // 1b2c0091610b40ad + FLDPQ 1024(R0), (F1, F2) // 1b001091610b40ad + FLDPQ 4104(R0), (F1, F2) + FLDPQ -4000(RSP), (F1, F2) // fb833ed1610b40ad + FLDPQ -1024(RSP), (F1, F2) // e10b60ad + FLDPQ (RSP), (F1, F2) // e10b40ad + FLDPQ 16(RSP), (F1, F2) // e18b40ad + FLDPQ -16(RSP), (F1, F2) // e18b7fad + FLDPQ.W 32(RSP), (F1, F2) // e10bc1ad + FLDPQ.P 32(RSP), (F1, F2) // e10bc1ac + FLDPQ 11(RSP), (F1, F2) // fb2f0091610b40ad + FLDPQ 1024(RSP), (F1, F2) // fb031091610b40ad + FLDPQ 4104(RSP), (F1, F2) + FLDPQ -31(R0), (F1, F2) // 1b7c00d1610b40ad + FLDPQ -4(R0), (F1, F2) // 1b1000d1610b40ad + FLDPQ x(SB), (F1, F2) + FLDPQ x+8(SB), (F1, F2) + FSTPQ (F3, F4), -4000(R5) // bb803ed1631300ad + FSTPQ (F3, F4), -1024(R5) // a31020ad + FSTPQ (F3, F4), (R5) // a31000ad + FSTPQ (F3, F4), 16(R5) // a39000ad + FSTPQ (F3, F4), -16(R5) // a3903fad + FSTPQ.W (F3, F4), 32(R5) // a31081ad + FSTPQ.P (F3, F4), 32(R5) // a31081ac + FSTPQ (F3, F4), 11(R5) // bb2c0091631300ad + FSTPQ (F3, F4), 1024(R5) // bb001091631300ad + FSTPQ (F3, F4), 4104(R5) + FSTPQ (F3, F4), -4000(RSP) // fb833ed1631300ad + FSTPQ (F3, F4), -1024(RSP) // e31320ad + FSTPQ (F3, F4), (RSP) // e31300ad + FSTPQ (F3, F4), 16(RSP) // e39300ad + FSTPQ (F3, F4), -16(RSP) // e3933fad + FSTPQ.W (F3, F4), 32(RSP) // e31381ad + FSTPQ.P (F3, F4), 32(RSP) // e31381ac + FSTPQ (F3, F4), 11(RSP) // fb2f0091631300ad + FSTPQ (F3, F4), 1024(RSP) // fb031091631300ad + FSTPQ (F3, F4), 4104(RSP) + FSTPQ (F3, F4), x(SB) + FSTPQ (F3, F4), x+8(SB) + // System Register MSR $1, SPSel // bf4100d5 MSR $9, DAIFSet // df4903d5 diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index e579f20836..9b4f42a8ff 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -109,6 +109,9 @@ TEXT errors(SB),$0 VREV16 V1.D1, V2.D1 // ERROR "invalid arrangement" VREV16 V1.B8, V2.B16 // ERROR "invalid arrangement" VREV16 V1.H4, V2.H4 // ERROR "invalid arrangement" + FLDPQ (R0), (R1, R2) // ERROR "invalid register pair" + FLDPQ (R1), (F2, F2) // ERROR "constrained unpredictable behavior" + FSTPQ (R1, R2), (R0) // ERROR "invalid register pair" FLDPD (R0), (R1, R2) // ERROR "invalid register pair" FLDPD (R1), (F2, F2) // ERROR "constrained unpredictable behavior" FLDPS (R2), (F3, F3) // ERROR "constrained unpredictable behavior" |