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| author | Cherry Zhang <cherryyz@google.com> | 2020-10-28 09:12:20 -0400 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2020-10-28 09:12:20 -0400 |
| commit | a16e30d162c1c7408db7821e7b9513cefa09c6ca (patch) | |
| tree | af752ba9ba44c547df39bb0af9bff79f610ba9d5 /src/cmd/asm/internal/asm/testdata/riscvenc.s | |
| parent | 91e4d2d57bc341dd82c98247117114c851380aef (diff) | |
| parent | cf6cfba4d5358404dd890f6025e573a4b2156543 (diff) | |
| download | go-a16e30d162c1c7408db7821e7b9513cefa09c6ca.tar.gz go-a16e30d162c1c7408db7821e7b9513cefa09c6ca.zip | |
[dev.link] all: merge branch 'master' into dev.linkdev.link
Clean merge.
Change-Id: Ia7b2808bc649790198d34c226a61d9e569084dc5
Diffstat (limited to 'src/cmd/asm/internal/asm/testdata/riscvenc.s')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscvenc.s | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s index 8d301f2dd5..e30a576473 100644 --- a/src/cmd/asm/internal/asm/testdata/riscvenc.s +++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s @@ -297,6 +297,13 @@ start: MOVW X5, (X6) // 23205300 MOVW X5, 4(X6) // 23225300 + MOVB X5, X6 // 1393820313538343 + MOVH X5, X6 // 1393020313530343 + MOVW X5, X6 // 1b830200 + MOVBU X5, X6 // 13f3f20f + MOVHU X5, X6 // 1393020313530303 + MOVWU X5, X6 // 1393020213530302 + MOVF 4(X5), F0 // 07a04200 MOVF F0, 4(X5) // 27a20200 MOVF F0, F1 // d3000020 @@ -318,7 +325,7 @@ start: // These jumps can get printed as jumps to 2 because they go to the // second instruction in the function (the first instruction is an // invisible stack pointer adjustment). - JMP start // JMP 2 // 6ff01fc5 + JMP start // JMP 2 // 6ff09fc2 JMP (X5) // 67800200 JMP 4(X5) // 67804200 @@ -331,16 +338,16 @@ start: JMP asmtest(SB) // 970f0000 // Branch pseudo-instructions - BEQZ X5, start // BEQZ X5, 2 // e38a02c2 - BGEZ X5, start // BGEZ X5, 2 // e3d802c2 - BGT X5, X6, start // BGT X5, X6, 2 // e3c662c2 - BGTU X5, X6, start // BGTU X5, X6, 2 // e3e462c2 - BGTZ X5, start // BGTZ X5, 2 // e34250c2 - BLE X5, X6, start // BLE X5, X6, 2 // e3d062c2 - BLEU X5, X6, start // BLEU X5, X6, 2 // e3fe62c0 - BLEZ X5, start // BLEZ X5, 2 // e35c50c0 - BLTZ X5, start // BLTZ X5, 2 // e3ca02c0 - BNEZ X5, start // BNEZ X5, 2 // e39802c0 + BEQZ X5, start // BEQZ X5, 2 // e38602c0 + BGEZ X5, start // BGEZ X5, 2 // e3d402c0 + BGT X5, X6, start // BGT X5, X6, 2 // e3c262c0 + BGTU X5, X6, start // BGTU X5, X6, 2 // e3e062c0 + BGTZ X5, start // BGTZ X5, 2 // e34e50be + BLE X5, X6, start // BLE X5, X6, 2 // e3dc62be + BLEU X5, X6, start // BLEU X5, X6, 2 // e3fa62be + BLEZ X5, start // BLEZ X5, 2 // e35850be + BLTZ X5, start // BLTZ X5, 2 // e3c602be + BNEZ X5, start // BNEZ X5, 2 // e39402be // Set pseudo-instructions SEQZ X15, X15 // 93b71700 |