diff options
| author | Lynn Boger <laboger@linux.vnet.ibm.com> | 2016-06-16 14:57:45 -0500 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2016-06-28 04:49:33 +0000 |
| commit | b75b0630fe6d8f66f937f78f15f540b5b6dab24f (patch) | |
| tree | 66c739955c6bf7643a8a6aa90a8c16ed51c57610 | |
| parent | 05ecf534566c0cd05b4afdaa9619522e4204328e (diff) | |
| download | go-b75b0630fe6d8f66f937f78f15f540b5b6dab24f.tar.gz go-b75b0630fe6d8f66f937f78f15f540b5b6dab24f.zip | |
runtime/internal/atomic: Use power5 compatible instructions for ppc64
This modifies a recent performance improvement to the
And8 and Or8 atomic functions which required both ppc64le
and ppc64 to use power8 instructions. Since then it was
decided that ppc64 (BE) should work for power5 and later.
This change uses instructions compatible with power5 for
ppc64 and uses power8 for ppc64le.
Fixes #16004
Change-Id: I623c75e8e6fd1fa063a53d250d86cdc9d0890dc7
Reviewed-on: https://go-review.googlesource.com/24181
Reviewed-by: Keith Randall <khr@golang.org>
Run-TryBot: Andrew Gerrand <adg@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
| -rw-r--r-- | src/runtime/internal/atomic/asm_ppc64x.s | 51 |
1 files changed, 47 insertions, 4 deletions
diff --git a/src/runtime/internal/atomic/asm_ppc64x.s b/src/runtime/internal/atomic/asm_ppc64x.s index a928e400d2..de4f895efd 100644 --- a/src/runtime/internal/atomic/asm_ppc64x.s +++ b/src/runtime/internal/atomic/asm_ppc64x.s @@ -161,28 +161,71 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-16 MOVD R4, 0(R3) RET -// void runtime∕internal∕atomic·Or8(byte volatile*, byte); +// void runtime∕internal∕atomic·Or8(byte volatile*, byte); TEXT runtime∕internal∕atomic·Or8(SB), NOSPLIT, $0-9 MOVD ptr+0(FP), R3 MOVBZ val+8(FP), R4 +#ifdef GOARCH_ppc64 + // Align ptr down to 4 bytes so we can use 32-bit load/store. + // R5 = (R3 << 0) & ~3 + RLDCR $0, R3, $~3, R5 + // Compute val shift. + // Big endian. ptr = ptr ^ 3 + XOR $3, R3 + // R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8) + RLDC $3, R3, $(3*8), R6 + // Shift val for aligned ptr. R4 = val << R6 + SLD R6, R4, R4 + SYNC + +again: + LWAR (R5), R6 + OR R4, R6 + STWCCC R6, (R5) + BNE again +#else SYNC again: LBAR (R3), R6 OR R4, R6 STBCCC R6, (R3) BNE again +#endif ISYNC RET -// void runtime∕internal∕atomic·And8(byte volatile*, byte); +// void runtime∕internal∕atomic·And8(byte volatile*, byte); TEXT runtime∕internal∕atomic·And8(SB), NOSPLIT, $0-9 MOVD ptr+0(FP), R3 MOVBZ val+8(FP), R4 +#ifdef GOARCH_ppc64 + // Align ptr down to 4 bytes so we can use 32-bit load/store. + // R5 = (R3 << 0) & ~3 + RLDCR $0, R3, $~3, R5 + // Compute val shift. + // Big endian. ptr = ptr ^ 3 + XOR $3, R3 + // R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8) + RLDC $3, R3, $(3*8), R6 + // Shift val for aligned ptr. R4 = val << R6 | ^(0xFF << R6) + MOVD $0xFF, R7 + SLD R6, R4 + SLD R6, R7 + XOR $-1, R7 + OR R7, R4 SYNC again: - LBAR (R3), R6 + LWAR (R5), R6 AND R4, R6 - STBCCC R6, (R3) + STWCCC R6, (R5) + BNE again +#else + SYNC +again: + LBAR (R3),R6 + AND R4,R6 + STBCCC R6,(R3) BNE again +#endif ISYNC RET |