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authorCherry Zhang <cherryyz@google.com>2016-08-04 06:57:34 -0400
committerCherry Zhang <cherryyz@google.com>2016-08-07 03:08:03 +0000
commit0484052358ffdfb64cd533b3ea55f7c2b9d0b7bd (patch)
tree9970070d3ef8a2fbfa441078188b8ba4cf960e5b
parent01ae4b1da4fd38c0cc5f370c958aa67735fdcd40 (diff)
downloadgo-0484052358ffdfb64cd533b3ea55f7c2b9d0b7bd.tar.gz
go-0484052358ffdfb64cd533b3ea55f7c2b9d0b7bd.zip
[dev.ssa] cmd/compile: remove flags from regMask
Reg allocator skips flag-typed values. Flag allocator uses the type and whether the op has "clobberFlags" set. Tested on AMD64, ARM, ARM64, 386. Passed 'toolstash -cmp' on AMD64. PPC64 is coded blindly. Change-Id: Ib1cc27efecef6a1bb27f7d7ed035a582660d244f Reviewed-on: https://go-review.googlesource.com/25480 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
Diffstat
-rw-r--r--src/cmd/compile/internal/ssa/config.go6
-rw-r--r--src/cmd/compile/internal/ssa/flagalloc.go4
-rw-r--r--src/cmd/compile/internal/ssa/gen/386Ops.go213
-rw-r--r--src/cmd/compile/internal/ssa/gen/AMD64Ops.go267
-rw-r--r--src/cmd/compile/internal/ssa/gen/ARM64Ops.go52
-rw-r--r--src/cmd/compile/internal/ssa/gen/ARMOps.go66
-rw-r--r--src/cmd/compile/internal/ssa/gen/PPC64Ops.go57
-rw-r--r--src/cmd/compile/internal/ssa/gen/main.go10
-rw-r--r--src/cmd/compile/internal/ssa/op.go1
-rw-r--r--src/cmd/compile/internal/ssa/opGen.go1777
-rw-r--r--src/cmd/compile/internal/ssa/regalloc.go4
11 files changed, 1030 insertions, 1427 deletions
diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go
index 58cecfdd49..1bfee3882f 100644
--- a/src/cmd/compile/internal/ssa/config.go
+++ b/src/cmd/compile/internal/ssa/config.go
@@ -22,7 +22,6 @@ type Config struct {
registers []Register // machine registers
gpRegMask regMask // general purpose integer register mask
fpRegMask regMask // floating point register mask
- flagRegMask regMask // flag register mask
FPReg int8 // register number of frame pointer, -1 if not used
hasGReg bool // has hardware g register
fe Frontend // callbacks into compiler frontend
@@ -137,7 +136,6 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
c.registers = registersAMD64[:]
c.gpRegMask = gpRegMaskAMD64
c.fpRegMask = fpRegMaskAMD64
- c.flagRegMask = flagRegMaskAMD64
c.FPReg = framepointerRegAMD64
c.hasGReg = false
case "386":
@@ -148,7 +146,6 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
c.registers = registers386[:]
c.gpRegMask = gpRegMask386
c.fpRegMask = fpRegMask386
- c.flagRegMask = flagRegMask386
c.FPReg = framepointerReg386
c.hasGReg = false
case "arm":
@@ -159,7 +156,6 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
c.registers = registersARM[:]
c.gpRegMask = gpRegMaskARM
c.fpRegMask = fpRegMaskARM
- c.flagRegMask = flagRegMaskARM
c.FPReg = framepointerRegARM
c.hasGReg = true
case "arm64":
@@ -170,7 +166,6 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
c.registers = registersARM64[:]
c.gpRegMask = gpRegMaskARM64
c.fpRegMask = fpRegMaskARM64
- c.flagRegMask = flagRegMaskARM64
c.FPReg = framepointerRegARM64
c.hasGReg = true
case "ppc64le":
@@ -181,7 +176,6 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
c.registers = registersPPC64[:]
c.gpRegMask = gpRegMaskPPC64
c.fpRegMask = fpRegMaskPPC64
- c.flagRegMask = flagRegMaskPPC64
c.FPReg = framepointerRegPPC64
c.noDuffDevice = true // TODO: Resolve PPC64 DuffDevice (has zero, but not copy)
c.hasGReg = true
diff --git a/src/cmd/compile/internal/ssa/flagalloc.go b/src/cmd/compile/internal/ssa/flagalloc.go
index 1aa82a3947..aefa81b5b3 100644
--- a/src/cmd/compile/internal/ssa/flagalloc.go
+++ b/src/cmd/compile/internal/ssa/flagalloc.go
@@ -31,7 +31,7 @@ func flagalloc(f *Func) {
if v == flag {
flag = nil
}
- if opcodeTable[v.Op].reg.clobbers&f.Config.flagRegMask != 0 {
+ if opcodeTable[v.Op].clobberFlags {
flag = nil
}
for _, a := range v.Args {
@@ -103,7 +103,7 @@ func flagalloc(f *Func) {
}
// Issue v.
b.Values = append(b.Values, v)
- if opcodeTable[v.Op].reg.clobbers&f.Config.flagRegMask != 0 {
+ if opcodeTable[v.Op].clobberFlags {
flag = nil
}
if v.Type.IsFlags() {
diff --git a/src/cmd/compile/internal/ssa/gen/386Ops.go b/src/cmd/compile/internal/ssa/gen/386Ops.go
index 49c4cd49e4..83db157d4f 100644
--- a/src/cmd/compile/internal/ssa/gen/386Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/386Ops.go
@@ -47,7 +47,6 @@ var regNames386 = []string{
// pseudo-registers
"SB",
- "FLAGS",
}
func init() {
@@ -81,45 +80,39 @@ func init() {
x7 = buildReg("X7")
gpsp = gp | buildReg("SP")
gpspsb = gpsp | buildReg("SB")
- flags = buildReg("FLAGS")
- callerSave = gp | fp | flags
+ callerSave = gp | fp
)
// Common slices of register masks
var (
- gponly = []regMask{gp}
- fponly = []regMask{fp}
- flagsonly = []regMask{flags}
+ gponly = []regMask{gp}
+ fponly = []regMask{fp}
)
// Common regInfo
var (
- gp01 = regInfo{inputs: []regMask{}, outputs: gponly}
- gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly, clobbers: flags}
- gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
- gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered
+ gp01 = regInfo{inputs: nil, outputs: gponly}
+ gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly}
+ gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly}
gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly}
- gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly, clobbers: flags}
- gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{flags, gp}}
- gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{flags, gp}}
- gp1carry1 = regInfo{inputs: []regMask{gp, flags}, outputs: gponly}
- gp2carry1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: gponly}
- gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
+ gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly}
+ gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{0, gp}}
+ gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{0, gp}}
+ gp1carry1 = regInfo{inputs: []regMask{gp}, outputs: gponly}
+ gp2carry1 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly}
+ gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly}
gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
- gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
- gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
- clobbers: dx | flags}
- gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
- clobbers: ax | flags}
- gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx},
- clobbers: ax | flags}
- gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}, clobbers: flags}
-
- gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
- gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
- flagsgp = regInfo{inputs: flagsonly, outputs: gponly}
-
- readflags = regInfo{inputs: flagsonly, outputs: gponly}
- flagsgpax = regInfo{inputs: flagsonly, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
+ gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}}
+ gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax}, clobbers: dx}
+ gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax}
+ gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx}, clobbers: ax}
+ gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}}
+
+ gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}}
+ gp1flags = regInfo{inputs: []regMask{gpsp}}
+ flagsgp = regInfo{inputs: nil, outputs: gponly}
+
+ readflags = regInfo{inputs: nil, outputs: gponly}
+ flagsgpax = regInfo{inputs: nil, clobbers: ax, outputs: []regMask{gp &^ ax}}
gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: gponly}
gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: gponly}
@@ -129,14 +122,14 @@ func init() {
gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}}
gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}}
- fp01 = regInfo{inputs: []regMask{}, outputs: fponly}
+ fp01 = regInfo{inputs: nil, outputs: fponly}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
fp21x7 = regInfo{inputs: []regMask{fp &^ x7, fp &^ x7},
clobbers: x7, outputs: []regMask{fp &^ x7}}
fpgp = regInfo{inputs: fponly, outputs: gponly}
gpfp = regInfo{inputs: gponly, outputs: fponly}
fp11 = regInfo{inputs: fponly, outputs: fponly}
- fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: flagsonly}
+ fp2flags = regInfo{inputs: []regMask{fp, fp}}
fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly}
fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly}
@@ -173,52 +166,52 @@ func init() {
{name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store
// binary ops
- {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true}, // arg0 + arg1
- {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32"}, // arg0 + auxint
+ {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1
+ {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32", clobberFlags: true}, // arg0 + auxint
- {name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1, generates <carry,result> pair
- {name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates <carry,result> pair
- {name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true}, // arg0+arg1+carry(arg2), where arg2 is flags
- {name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true}, // arg0+auxint+carry(arg1), where arg1 is flags
+ {name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1, generates <carry,result> pair
+ {name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates <carry,result> pair
+ {name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0+arg1+carry(arg2), where arg2 is flags
+ {name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0+auxint+carry(arg1), where arg1 is flags
- {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true}, // arg0 - arg1
- {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0 - auxint
+ {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, // arg0 - arg1
+ {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint
- {name: "SUBLcarry", argLength: 2, reg: gp21carry, asm: "SUBL", resultInArg0: true}, // arg0-arg1, generates <borrow,result> pair
- {name: "SUBLconstcarry", argLength: 1, reg: gp11carry, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0-auxint, generates <borrow,result> pair
- {name: "SBBL", argLength: 3, reg: gp2carry1, asm: "SBBL", resultInArg0: true}, // arg0-arg1-borrow(arg2), where arg2 is flags
- {name: "SBBLconst", argLength: 2, reg: gp1carry1, asm: "SBBL", aux: "Int32", resultInArg0: true}, // arg0-auxint-borrow(arg1), where arg1 is flags
+ {name: "SUBLcarry", argLength: 2, reg: gp21carry, asm: "SUBL", resultInArg0: true}, // arg0-arg1, generates <borrow,result> pair
+ {name: "SUBLconstcarry", argLength: 1, reg: gp11carry, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0-auxint, generates <borrow,result> pair
+ {name: "SBBL", argLength: 3, reg: gp2carry1, asm: "SBBL", resultInArg0: true, clobberFlags: true}, // arg0-arg1-borrow(arg2), where arg2 is flags
+ {name: "SBBLconst", argLength: 2, reg: gp1carry1, asm: "SBBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0-auxint-borrow(arg1), where arg1 is flags
- {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true}, // arg0 * arg1
- {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true}, // arg0 * auxint
+ {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1
+ {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 * auxint
- {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
- {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL"}, // (arg0 * arg1) >> width
- {name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
- {name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
- {name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW"}, // (arg0 * arg1) >> width
- {name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB"}, // (arg0 * arg1) >> width
+ {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB", clobberFlags: true}, // (arg0 * arg1) >> width
- {name: "MULLQU", argLength: 2, reg: gp21mul, asm: "MULL"}, // arg0 * arg1, high 32 in result[0], low 32 in result[1]
+ {name: "MULLQU", argLength: 2, reg: gp21mul, asm: "MULL", clobberFlags: true}, // arg0 * arg1, high 32 in result[0], low 32 in result[1]
- {name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL"}, // arg0 / arg1
- {name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW"}, // arg0 / arg1
- {name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL"}, // arg0 / arg1
- {name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW"}, // arg0 / arg1
+ {name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL", clobberFlags: true}, // arg0 / arg1
+ {name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW", clobberFlags: true}, // arg0 / arg1
+ {name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL", clobberFlags: true}, // arg0 / arg1
+ {name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW", clobberFlags: true}, // arg0 / arg1
- {name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL"}, // arg0 % arg1
- {name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW"}, // arg0 % arg1
- {name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL"}, // arg0 % arg1
- {name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW"}, // arg0 % arg1
+ {name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL", clobberFlags: true}, // arg0 % arg1
+ {name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW", clobberFlags: true}, // arg0 % arg1
+ {name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL", clobberFlags: true}, // arg0 % arg1
+ {name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW", clobberFlags: true}, // arg0 % arg1
- {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true}, // arg0 & arg1
- {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true}, // arg0 & auxint
+ {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1
+ {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint
- {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true}, // arg0 | arg1
- {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true}, // arg0 | auxint
+ {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1
+ {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint
- {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true}, // arg0 ^ arg1
- {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true}, // arg0 ^ auxint
+ {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1
+ {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
{name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1
@@ -237,40 +230,40 @@ func init() {
{name: "TESTWconst", argLength: 1, reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0
{name: "TESTBconst", argLength: 1, reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0
- {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true}, // arg0 << arg1, shift amount is mod 32
- {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true}, // arg0 << auxint, shift amount 0-31
+ {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true}, // arg0 << arg1, shift amount is mod 32
+ {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 << auxint, shift amount 0-31
// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
- {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
- {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
- {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
+ {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
+ {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
+ {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
- {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
- {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
- {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
+ {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
+ {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
+ {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
- {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-31
- {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-15
- {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-7
+ {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-31
+ {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15
+ {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7
// unary ops
- {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true}, // -arg0
+ {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true}, // -arg0
- {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true}, // ^arg0
+ {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true, clobberFlags: true}, // ^arg0
- {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL"}, // arg0 # of low-order zeroes ; undef if zero
- {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW"}, // arg0 # of low-order zeroes ; undef if zero
+ {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero
+ {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero
- {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL"}, // arg0 # of high-order zeroes ; undef if zero
- {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW"}, // arg0 # of high-order zeroes ; undef if zero
+ {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero
+ {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero
- {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true}, // arg0 swap bytes
+ {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true, clobberFlags: true}, // arg0 swap bytes
{name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0)
@@ -290,18 +283,18 @@ func init() {
// Need different opcodes for floating point conditions because
// any comparison involving a NaN is always FALSE and thus
// the patterns for inverting conditions cannot be used.
- {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ"}, // extract == condition from arg0
- {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE"}, // extract != condition from arg0
- {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0
- {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0
+ {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ", clobberFlags: true}, // extract == condition from arg0
+ {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE", clobberFlags: true}, // extract != condition from arg0
+ {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0
+ {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0
{name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0
{name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0
- {name: "MOVBLSX", argLength: 1, reg: gp11nf, asm: "MOVBLSX"}, // sign extend arg0 from int8 to int32
- {name: "MOVBLZX", argLength: 1, reg: gp11nf, asm: "MOVBLZX"}, // zero extend arg0 from int8 to int32
- {name: "MOVWLSX", argLength: 1, reg: gp11nf, asm: "MOVWLSX"}, // sign extend arg0 from int16 to int32
- {name: "MOVWLZX", argLength: 1, reg: gp11nf, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int32
+ {name: "MOVBLSX", argLength: 1, reg: gp11, asm: "MOVBLSX"}, // sign extend arg0 from int8 to int32
+ {name: "MOVBLZX", argLength: 1, reg: gp11, asm: "MOVBLZX"}, // zero extend arg0 from int8 to int32
+ {name: "MOVWLSX", argLength: 1, reg: gp11, asm: "MOVWLSX"}, // sign extend arg0 from int16 to int32
+ {name: "MOVWLZX", argLength: 1, reg: gp11, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int32
{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint
@@ -369,7 +362,7 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("AX")},
- clobbers: buildReg("DI FLAGS"),
+ clobbers: buildReg("DI"),
},
},
@@ -387,11 +380,11 @@ func init() {
},
},
- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
- {name: "CALLclosure", argLength: 3, reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
- {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+ {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
+ {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+ {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// arg0 = destination pointer
// arg1 = source pointer
@@ -404,8 +397,9 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("SI")},
- clobbers: buildReg("DI SI CX FLAGS"), // uses CX as a temporary
+ clobbers: buildReg("DI SI CX"), // uses CX as a temporary
},
+ clobberFlags: true,
},
// arg0 = destination pointer
@@ -436,14 +430,14 @@ func init() {
// use of DX (the closure pointer)
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("DX")}}},
//arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
- {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}, clobbers: flags}},
+ {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}}, clobberFlags: true},
// MOVLconvert converts between pointers and integers.
// We have a special op for this so as to not confuse GC
// (particularly stack maps). It takes a memory arg so it
// gets correctly ordered with respect to GC safepoints.
// arg0=ptr/int arg1=mem, output=int/ptr
- {name: "MOVLconvert", argLength: 2, reg: gp11nf, asm: "MOVL"},
+ {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL"},
// Constant flag values. For any comparison, there are 5 possible
// outcomes: the three from the signed total order (<,==,>) and the
@@ -485,7 +479,6 @@ func init() {
regnames: regNames386,
gpregmask: gp,
fpregmask: fp,
- flagmask: flags,
framepointerreg: int8(num["BP"]),
})
}
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index 5772cada9c..7319fffa8e 100644
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -64,7 +64,6 @@ var regNamesAMD64 = []string{
// pseudo-registers
"SB",
- "FLAGS",
}
func init() {
@@ -98,41 +97,36 @@ func init() {
fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15")
gpsp = gp | buildReg("SP")
gpspsb = gpsp | buildReg("SB")
- flags = buildReg("FLAGS")
- callerSave = gp | fp | flags
+ callerSave = gp | fp
)
// Common slices of register masks
var (
- gponly = []regMask{gp}
- fponly = []regMask{fp}
- flagsonly = []regMask{flags}
+ gponly = []regMask{gp}
+ fponly = []regMask{fp}
)
// Common regInfo
var (
- gp01 = regInfo{inputs: []regMask{}, outputs: gponly}
- gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly, clobbers: flags}
- gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
- gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered
+ gp01 = regInfo{inputs: nil, outputs: gponly}
+ gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly}
+ gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly}
gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly}
- gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly, clobbers: flags}
- gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
+ gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly}
+ gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly}
gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
- gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
- gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax, dx},
- clobbers: flags}
- gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
- clobbers: ax | flags}
+ gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}}
+ gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax, dx}}
+ gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax}
- gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
- gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
- flagsgp = regInfo{inputs: flagsonly, outputs: gponly}
+ gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}}
+ gp1flags = regInfo{inputs: []regMask{gpsp}}
+ flagsgp = regInfo{inputs: nil, outputs: gponly}
// for CMOVconst -- uses AX to hold constant temporary.
- gp1flagsgp = regInfo{inputs: []regMask{gp &^ ax, flags}, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
+ gp1flagsgp = regInfo{inputs: []regMask{gp &^ ax}, clobbers: ax, outputs: []regMask{gp &^ ax}}
- readflags = regInfo{inputs: flagsonly, outputs: gponly}
- flagsgpax = regInfo{inputs: flagsonly, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
+ readflags = regInfo{inputs: nil, outputs: gponly}
+ flagsgpax = regInfo{inputs: nil, clobbers: ax, outputs: []regMask{gp &^ ax}}
gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: gponly}
gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: gponly}
@@ -142,14 +136,14 @@ func init() {
gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}}
gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}}
- fp01 = regInfo{inputs: []regMask{}, outputs: fponly}
+ fp01 = regInfo{inputs: nil, outputs: fponly}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},
clobbers: x15, outputs: []regMask{fp &^ x15}}
fpgp = regInfo{inputs: fponly, outputs: gponly}
gpfp = regInfo{inputs: gponly, outputs: fponly}
fp11 = regInfo{inputs: fponly, outputs: fponly}
- fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: flagsonly}
+ fp2flags = regInfo{inputs: []regMask{fp, fp}}
fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly}
fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly}
@@ -186,53 +180,53 @@ func init() {
{name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store
// binary ops
- {name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true}, // arg0 + arg1
- {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true}, // arg0 + arg1
- {name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
- {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
-
- {name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ", resultInArg0: true}, // arg0 - arg1
- {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true}, // arg0 - arg1
- {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64", resultInArg0: true}, // arg0 - auxint
- {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0 - auxint
-
- {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ", commutative: true, resultInArg0: true}, // arg0 * arg1
- {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true}, // arg0 * arg1
- {name: "MULQconst", argLength: 1, reg: gp11, asm: "IMULQ", aux: "Int64", resultInArg0: true}, // arg0 * auxint
- {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true}, // arg0 * auxint
-
- {name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ"}, // (arg0 * arg1) >> width
- {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
- {name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
- {name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
- {name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ"}, // (arg0 * arg1) >> width
- {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL"}, // (arg0 * arg1) >> width
- {name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW"}, // (arg0 * arg1) >> width
- {name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB"}, // (arg0 * arg1) >> width
-
- {name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
-
- {name: "DIVQ", argLength: 2, reg: gp11div, typ: "(Int64,Int64)", asm: "IDIVQ"}, // [arg0 / arg1, arg0 % arg1]
- {name: "DIVL", argLength: 2, reg: gp11div, typ: "(Int32,Int32)", asm: "IDIVL"}, // [arg0 / arg1, arg0 % arg1]
- {name: "DIVW", argLength: 2, reg: gp11div, typ: "(Int16,Int16)", asm: "IDIVW"}, // [arg0 / arg1, arg0 % arg1]
- {name: "DIVQU", argLength: 2, reg: gp11div, typ: "(UInt64,UInt64)", asm: "DIVQ"}, // [arg0 / arg1, arg0 % arg1]
- {name: "DIVLU", argLength: 2, reg: gp11div, typ: "(UInt32,UInt32)", asm: "DIVL"}, // [arg0 / arg1, arg0 % arg1]
- {name: "DIVWU", argLength: 2, reg: gp11div, typ: "(UInt16,UInt16)", asm: "DIVW"}, // [arg0 / arg1, arg0 % arg1]
-
- {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true}, // arg0 & arg1
- {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true}, // arg0 & arg1
- {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64", resultInArg0: true}, // arg0 & auxint
- {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true}, // arg0 & auxint
-
- {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ", commutative: true, resultInArg0: true}, // arg0 | arg1
- {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true}, // arg0 | arg1
- {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64", resultInArg0: true}, // arg0 | auxint
- {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true}, // arg0 | auxint
-
- {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ", commutative: true, resultInArg0: true}, // arg0 ^ arg1
- {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true}, // arg0 ^ arg1
- {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64", resultInArg0: true}, // arg0 ^ auxint
- {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true}, // arg0 ^ auxint
+ {name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true, clobberFlags: true}, // arg0 + arg1
+ {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1
+ {name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int64", typ: "UInt64", clobberFlags: true}, // arg0 + auxint
+ {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", clobberFlags: true}, // arg0 + auxint
+
+ {name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ", resultInArg0: true, clobberFlags: true}, // arg0 - arg1
+ {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, // arg0 - arg1
+ {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 - auxint
+ {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint
+
+ {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1
+ {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1
+ {name: "MULQconst", argLength: 1, reg: gp11, asm: "IMULQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 * auxint
+ {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 * auxint
+
+ {name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW", clobberFlags: true}, // (arg0 * arg1) >> width
+ {name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB", clobberFlags: true}, // (arg0 * arg1) >> width
+
+ {name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
+
+ {name: "DIVQ", argLength: 2, reg: gp11div, typ: "(Int64,Int64)", asm: "IDIVQ", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+ {name: "DIVL", argLength: 2, reg: gp11div, typ: "(Int32,Int32)", asm: "IDIVL", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+ {name: "DIVW", argLength: 2, reg: gp11div, typ: "(Int16,Int16)", asm: "IDIVW", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+ {name: "DIVQU", argLength: 2, reg: gp11div, typ: "(UInt64,UInt64)", asm: "DIVQ", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+ {name: "DIVLU", argLength: 2, reg: gp11div, typ: "(UInt32,UInt32)", asm: "DIVL", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+ {name: "DIVWU", argLength: 2, reg: gp11div, typ: "(UInt16,UInt16)", asm: "DIVW", clobberFlags: true}, // [arg0 / arg1, arg0 % arg1]
+
+ {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1
+ {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1
+ {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 & auxint
+ {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint
+
+ {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1
+ {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1
+ {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 | auxint
+ {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint
+
+ {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1
+ {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1
+ {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
+ {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
{name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
@@ -255,60 +249,60 @@ func init() {
{name: "TESTWconst", argLength: 1, reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0
{name: "TESTBconst", argLength: 1, reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0
- {name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ", resultInArg0: true}, // arg0 << arg1, shift amount is mod 64
- {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true}, // arg0 << arg1, shift amount is mod 32
- {name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64", resultInArg0: true}, // arg0 << auxint, shift amount 0-63
- {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true}, // arg0 << auxint, shift amount 0-31
+ {name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ", resultInArg0: true, clobberFlags: true}, // arg0 << arg1, shift amount is mod 64
+ {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true}, // arg0 << arg1, shift amount is mod 32
+ {name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 << auxint, shift amount 0-63
+ {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 << auxint, shift amount 0-31
// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
- {name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 64
- {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true}, // unsigned arg0 >> arg1, shift amount is mod 32
- {name: "SHRQconst", argLength: 1, reg: gp11, asm: "SHRQ", aux: "Int64", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-63
- {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
- {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
- {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true}, // unsigned arg0 >> auxint, shift amount 0-31
-
- {name: "SARQ", argLength: 2, reg: gp21shift, asm: "SARQ", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 64
- {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true}, // signed arg0 >> arg1, shift amount is mod 32
- {name: "SARQconst", argLength: 1, reg: gp11, asm: "SARQ", aux: "Int64", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-63
- {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
- {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
- {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true}, // signed arg0 >> auxint, shift amount 0-31
-
- {name: "ROLQconst", argLength: 1, reg: gp11, asm: "ROLQ", aux: "Int64", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-63
- {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-31
- {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-15
- {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true}, // arg0 rotate left auxint, rotate amount 0-7
+ {name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 64
+ {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32
+ {name: "SHRQconst", argLength: 1, reg: gp11, asm: "SHRQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-63
+ {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
+ {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
+ {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
+
+ {name: "SARQ", argLength: 2, reg: gp21shift, asm: "SARQ", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 64
+ {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
+ {name: "SARQconst", argLength: 1, reg: gp11, asm: "SARQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-63
+ {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
+ {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
+ {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
+
+ {name: "ROLQconst", argLength: 1, reg: gp11, asm: "ROLQ", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-63
+ {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-31
+ {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15
+ {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7
// unary ops
- {name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ", resultInArg0: true}, // -arg0
- {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true}, // -arg0
+ {name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ", resultInArg0: true, clobberFlags: true}, // -arg0
+ {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true}, // -arg0
- {name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ", resultInArg0: true}, // ^arg0
- {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true}, // ^arg0
+ {name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ", resultInArg0: true, clobberFlags: true}, // ^arg0
+ {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true, clobberFlags: true}, // ^arg0
- {name: "BSFQ", argLength: 1, reg: gp11, asm: "BSFQ"}, // arg0 # of low-order zeroes ; undef if zero
- {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL"}, // arg0 # of low-order zeroes ; undef if zero
- {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW"}, // arg0 # of low-order zeroes ; undef if zero
+ {name: "BSFQ", argLength: 1, reg: gp11, asm: "BSFQ", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero
+ {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero
+ {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero
- {name: "BSRQ", argLength: 1, reg: gp11, asm: "BSRQ"}, // arg0 # of high-order zeroes ; undef if zero
- {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL"}, // arg0 # of high-order zeroes ; undef if zero
- {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW"}, // arg0 # of high-order zeroes ; undef if zero
+ {name: "BSRQ", argLength: 1, reg: gp11, asm: "BSRQ", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero
+ {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero
+ {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero
// Note ASM for ops moves whole register
- {name: "CMOVQEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVQEQ", typ: "UInt64", aux: "Int64", resultInArg0: true}, // replace arg0 w/ constant if Z set
- {name: "CMOVLEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLEQ", typ: "UInt32", aux: "Int32", resultInArg0: true}, // replace arg0 w/ constant if Z set
- {name: "CMOVWEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLEQ", typ: "UInt16", aux: "Int16", resultInArg0: true}, // replace arg0 w/ constant if Z set
- {name: "CMOVQNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVQNE", typ: "UInt64", aux: "Int64", resultInArg0: true}, // replace arg0 w/ constant if Z not set
- {name: "CMOVLNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLNE", typ: "UInt32", aux: "Int32", resultInArg0: true}, // replace arg0 w/ constant if Z not set
- {name: "CMOVWNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLNE", typ: "UInt16", aux: "Int16", resultInArg0: true}, // replace arg0 w/ constant if Z not set
+ {name: "CMOVQEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVQEQ", typ: "UInt64", aux: "Int64", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z set
+ {name: "CMOVLEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLEQ", typ: "UInt32", aux: "Int32", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z set
+ {name: "CMOVWEQconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLEQ", typ: "UInt16", aux: "Int16", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z set
+ {name: "CMOVQNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVQNE", typ: "UInt64", aux: "Int64", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z not set
+ {name: "CMOVLNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLNE", typ: "UInt32", aux: "Int32", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z not set
+ {name: "CMOVWNEconst", argLength: 2, reg: gp1flagsgp, asm: "CMOVLNE", typ: "UInt16", aux: "Int16", resultInArg0: true, clobberFlags: true}, // replace arg0 w/ constant if Z not set
- {name: "BSWAPQ", argLength: 1, reg: gp11, asm: "BSWAPQ", resultInArg0: true}, // arg0 swap bytes
- {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true}, // arg0 swap bytes
+ {name: "BSWAPQ", argLength: 1, reg: gp11, asm: "BSWAPQ", resultInArg0: true, clobberFlags: true}, // arg0 swap bytes
+ {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true, clobberFlags: true}, // arg0 swap bytes
{name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0)
@@ -329,20 +323,20 @@ func init() {
// Need different opcodes for floating point conditions because
// any comparison involving a NaN is always FALSE and thus
// the patterns for inverting conditions cannot be used.
- {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ"}, // extract == condition from arg0
- {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE"}, // extract != condition from arg0
- {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0
- {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0
+ {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ", clobberFlags: true}, // extract == condition from arg0
+ {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE", clobberFlags: true}, // extract != condition from arg0
+ {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0
+ {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0
{name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0
{name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0
- {name: "MOVBQSX", argLength: 1, reg: gp11nf, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64
- {name: "MOVBQZX", argLength: 1, reg: gp11nf, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64
- {name: "MOVWQSX", argLength: 1, reg: gp11nf, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64
- {name: "MOVWQZX", argLength: 1, reg: gp11nf, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64
- {name: "MOVLQSX", argLength: 1, reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
- {name: "MOVLQZX", argLength: 1, reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
+ {name: "MOVBQSX", argLength: 1, reg: gp11, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64
+ {name: "MOVBQZX", argLength: 1, reg: gp11, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64
+ {name: "MOVWQSX", argLength: 1, reg: gp11, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64
+ {name: "MOVWQZX", argLength: 1, reg: gp11, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64
+ {name: "MOVLQSX", argLength: 1, reg: gp11, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
+ {name: "MOVLQZX", argLength: 1, reg: gp11, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint
{name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint
@@ -427,8 +421,9 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("X0")},
- clobbers: buildReg("DI FLAGS"),
+ clobbers: buildReg("DI"),
},
+ clobberFlags: true,
},
{name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128", aux: "Int128", rematerializeable: true},
@@ -446,11 +441,11 @@ func init() {
},
},
- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
- {name: "CALLclosure", argLength: 3, reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
- {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+ {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
+ {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+ {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// arg0 = destination pointer
// arg1 = source pointer
@@ -463,8 +458,9 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("SI")},
- clobbers: buildReg("DI SI X0 FLAGS"), // uses X0 as a temporary
+ clobbers: buildReg("DI SI X0"), // uses X0 as a temporary
},
+ clobberFlags: true,
},
// arg0 = destination pointer
@@ -495,14 +491,14 @@ func init() {
// use of DX (the closure pointer)
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("DX")}}},
//arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
- {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}, clobbers: flags}},
+ {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}}, clobberFlags: true},
// MOVQconvert converts between pointers and integers.
// We have a special op for this so as to not confuse GC
// (particularly stack maps). It takes a memory arg so it
// gets correctly ordered with respect to GC safepoints.
// arg0=ptr/int arg1=mem, output=int/ptr
- {name: "MOVQconvert", argLength: 2, reg: gp11nf, asm: "MOVQ"},
+ {name: "MOVQconvert", argLength: 2, reg: gp11, asm: "MOVQ"},
// Constant flag values. For any comparison, there are 5 possible
// outcomes: the three from the signed total order (<,==,>) and the
@@ -544,7 +540,6 @@ func init() {
regnames: regNamesAMD64,
gpregmask: gp,
fpregmask: fp,
- flagmask: flags,
framepointerreg: int8(num["BP"]),
})
}
diff --git a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go
index e6ffe13663..9c3453faaa 100644
--- a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go
@@ -97,7 +97,6 @@ var regNamesARM64 = []string{
"F31", // 2.0
// pseudo-registers
- "FLAGS",
"SB",
}
@@ -129,39 +128,37 @@ func init() {
gpsp = gp | buildReg("SP")
gpspg = gpg | buildReg("SP")
gpspsbg = gpspg | buildReg("SB")
- flags = buildReg("FLAGS")
fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27")
- callerSave = gp | fp | flags | buildReg("g") // runtime.setg (and anything calling it) may clobber g
+ callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g
)
// Common regInfo
var (
- gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
+ gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
- gp1flags = regInfo{inputs: []regMask{gpg}, outputs: []regMask{flags}}
- //gp1flags1 = regInfo{inputs: []regMask{gp, flags}, outputs: []regMask{gp}}
- gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
- //gp21cf = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: flags} // cf: clobbers flags
- gp2flags = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{flags}}
- gp2flags1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: []regMask{gp}}
+ gp1flags = regInfo{inputs: []regMask{gpg}}
+ //gp1flags1 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}
+ gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
+ gp2flags = regInfo{inputs: []regMask{gpg, gpg}}
+ gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
//gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}}
//gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
- //gp3flags = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{flags}}
- //gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp, flags}, outputs: []regMask{gp}}
+ //gp3flags = regInfo{inputs: []regMask{gp, gp, gp}}
+ //gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
- gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{}}
+ gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
//gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
- //gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{}}
- fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}}
+ //gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}}
+ fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
- //fp1flags = regInfo{inputs: []regMask{fp}, outputs: []regMask{flags}}
+ //fp1flags = regInfo{inputs: []regMask{fp}}
fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}}
gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
- fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{flags}}
+ fp2flags = regInfo{inputs: []regMask{fp, fp}}
fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
- fpstore = regInfo{inputs: []regMask{gpspsbg, fp}, outputs: []regMask{}}
- readflags = regInfo{inputs: []regMask{flags}, outputs: []regMask{gp}}
+ fpstore = regInfo{inputs: []regMask{gpspsbg, fp}}
+ readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
)
ops := []opData{
// binary ops
@@ -287,11 +284,11 @@ func init() {
{name: "CSELULT", argLength: 3, reg: gp2flags1, asm: "CSEL"}, // returns arg0 if flags indicates unsigned LT, arg1 otherwise, arg2=flags
// function calls
- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
- {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R26"), 0}, clobbers: callerSave}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
- {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+ {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
+ {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R26"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+ {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// pseudo-ops
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}}, // panic if arg0 is nil. arg1=mem.
@@ -340,8 +337,9 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("R16"), gp},
- clobbers: buildReg("R16 FLAGS"),
+ clobbers: buildReg("R16"),
},
+ clobberFlags: true,
},
// large move
@@ -363,8 +361,9 @@ func init() {
argLength: 4,
reg: regInfo{
inputs: []regMask{buildReg("R17"), buildReg("R16"), gp},
- clobbers: buildReg("R16 R17 FLAGS"),
+ clobbers: buildReg("R16 R17"),
},
+ clobberFlags: true,
},
// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
@@ -419,7 +418,6 @@ func init() {
regnames: regNamesARM64,
gpregmask: gp,
fpregmask: fp,
- flagmask: flags,
framepointerreg: -1, // not used
})
}
diff --git a/src/cmd/compile/internal/ssa/gen/ARMOps.go b/src/cmd/compile/internal/ssa/gen/ARMOps.go
index 865dc1034e..f1774c6be0 100644
--- a/src/cmd/compile/internal/ssa/gen/ARMOps.go
+++ b/src/cmd/compile/internal/ssa/gen/ARMOps.go
@@ -61,7 +61,6 @@ var regNamesARM = []string{
"F15", // tmp
// pseudo-registers
- "FLAGS",
"SB",
}
@@ -93,42 +92,40 @@ func init() {
gpsp = gp | buildReg("SP")
gpspg = gpg | buildReg("SP")
gpspsbg = gpspg | buildReg("SB")
- flags = buildReg("FLAGS")
fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15")
- callerSave = gp | fp | flags | buildReg("g") // runtime.setg (and anything calling it) may clobber g
+ callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g
)
// Common regInfo
var (
- gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
+ gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
- gp11carry = regInfo{inputs: []regMask{gpg}, outputs: []regMask{flags, gp}}
+ gp11carry = regInfo{inputs: []regMask{gpg}, outputs: []regMask{0, gp}}
gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
- gp1flags = regInfo{inputs: []regMask{gpg}, outputs: []regMask{flags}}
- gp1flags1 = regInfo{inputs: []regMask{gp, flags}, outputs: []regMask{gp}}
+ gp1flags = regInfo{inputs: []regMask{gpg}}
+ gp1flags1 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}
gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
- gp21cf = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: flags} // cf: clobbers flags
- gp21carry = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{flags, gp}}
- gp2flags = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{flags}}
- gp2flags1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: []regMask{gp}}
+ gp21carry = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{0, gp}}
+ gp2flags = regInfo{inputs: []regMask{gpg, gpg}}
+ gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}}
gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
- gp31carry = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{flags, gp}}
- gp3flags = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{flags}}
- gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp, flags}, outputs: []regMask{gp}}
+ gp31carry = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{0, gp}}
+ gp3flags = regInfo{inputs: []regMask{gp, gp, gp}}
+ gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
- gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{}}
+ gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
- gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{}}
- fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}}
+ gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}}
+ fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
- fp1flags = regInfo{inputs: []regMask{fp}, outputs: []regMask{flags}}
+ fp1flags = regInfo{inputs: []regMask{fp}}
fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}}
gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
- fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{flags}}
+ fp2flags = regInfo{inputs: []regMask{fp, fp}}
fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
- fpstore = regInfo{inputs: []regMask{gpspsbg, fp}, outputs: []regMask{}}
- readflags = regInfo{inputs: []regMask{flags}, outputs: []regMask{gp}}
+ fpstore = regInfo{inputs: []regMask{gpspsbg, fp}}
+ readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
)
ops := []opData{
// binary ops
@@ -141,10 +138,10 @@ func init() {
{name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1
{name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true}, // (arg0 * arg1) >> 32, signed
{name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true}, // (arg0 * arg1) >> 32, unsigned
- {name: "DIV", argLength: 2, reg: gp21cf, asm: "DIV"}, // arg0 / arg1, signed, soft div clobbers flags
- {name: "DIVU", argLength: 2, reg: gp21cf, asm: "DIVU"}, // arg0 / arg1, unsighed
- {name: "MOD", argLength: 2, reg: gp21cf, asm: "MOD"}, // arg0 % arg1, signed
- {name: "MODU", argLength: 2, reg: gp21cf, asm: "MODU"}, // arg0 % arg1, unsigned
+ {name: "DIV", argLength: 2, reg: gp21, asm: "DIV", clobberFlags: true}, // arg0 / arg1, signed, soft div clobbers flags
+ {name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", clobberFlags: true}, // arg0 / arg1, unsighed
+ {name: "MOD", argLength: 2, reg: gp21, asm: "MOD", clobberFlags: true}, // arg0 % arg1, signed
+ {name: "MODU", argLength: 2, reg: gp21, asm: "MODU", clobberFlags: true}, // arg0 % arg1, unsigned
{name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true}, // arg0 + arg1, set carry flag
{name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag
@@ -190,7 +187,7 @@ func init() {
{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt
{name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 256
{name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned
- {name: "SRA", argLength: 2, reg: gp21cf, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 256
+ {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 256
{name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed
{name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits
@@ -363,11 +360,11 @@ func init() {
{name: "SRAcond", argLength: 3, reg: gp2flags1, asm: "SRA"}, // arg0 >> 31 if flags indicates HS, arg0 >> arg1 otherwise, signed shift, arg2=flags
// function calls
- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
- {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R7"), 0}, clobbers: callerSave}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
- {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+ {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
+ {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R7"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+ {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// pseudo-ops
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}}, // panic if arg0 is nil. arg1=mem.
@@ -430,8 +427,9 @@ func init() {
argLength: 4,
reg: regInfo{
inputs: []regMask{buildReg("R1"), gp, gp},
- clobbers: buildReg("R1 FLAGS"),
+ clobbers: buildReg("R1"),
},
+ clobberFlags: true,
},
// large or unaligned move
@@ -450,8 +448,9 @@ func init() {
argLength: 4,
reg: regInfo{
inputs: []regMask{buildReg("R2"), buildReg("R1"), gp},
- clobbers: buildReg("R1 R2 FLAGS"),
+ clobbers: buildReg("R1 R2"),
},
+ clobberFlags: true,
},
// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
@@ -506,7 +505,6 @@ func init() {
regnames: regNamesARM,
gpregmask: gp,
fpregmask: fp,
- flagmask: flags,
framepointerreg: -1, // not used
})
}
diff --git a/src/cmd/compile/internal/ssa/gen/PPC64Ops.go b/src/cmd/compile/internal/ssa/gen/PPC64Ops.go
index 335780cda8..a24996ace4 100644
--- a/src/cmd/compile/internal/ssa/gen/PPC64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/PPC64Ops.go
@@ -92,7 +92,7 @@ var regNamesPPC64 = []string{
// "CR6",
// "CR7",
- "CR",
+ // "CR",
// "XER",
// "LR",
// "CTR",
@@ -125,28 +125,28 @@ func init() {
sp = buildReg("SP")
sb = buildReg("SB")
// gr = buildReg("g")
- cr = buildReg("CR")
+ //cr = buildReg("CR")
//ctr = buildReg("CTR")
//lr = buildReg("LR")
tmp = buildReg("R31")
ctxt = buildReg("R11")
// tls = buildReg("R13")
- gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
+ gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
- gp1cr = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{cr}}
- gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{cr}}
- crgp = regInfo{inputs: []regMask{cr}, outputs: []regMask{gp}}
+ gp1cr = regInfo{inputs: []regMask{gp | sp | sb}}
+ gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}}
+ crgp = regInfo{inputs: nil, outputs: []regMask{gp}}
gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
- gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{}}
- gpstorezero = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{}} // ppc64.REGZERO is reserved zero value
- fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}}
+ gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}}
+ gpstorezero = regInfo{inputs: []regMask{gp | sp | sb}} // ppc64.REGZERO is reserved zero value
+ fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
// fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
- fp2cr = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{cr}}
+ fp2cr = regInfo{inputs: []regMask{fp, fp}}
fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}}
- fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}, outputs: []regMask{}}
- callerSave = regMask(gp | fp | cr)
+ fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}}
+ callerSave = regMask(gp | fp)
)
ops := []opData{
{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
@@ -175,8 +175,8 @@ func init() {
{name: "SLD", argLength: 2, reg: gp21, asm: "SLD"}, // arg0 << arg1, 64 bits (0 if arg1 & 64 != 0)
{name: "SLW", argLength: 2, reg: gp21, asm: "SLW"}, // arg0 << arg1, 32 bits (0 if arg1 & 32 != 0)
- {name: "ADDconstForCarry", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{cr}, clobbers: tmp}, aux: "Int16", asm: "ADDC", typ: "Flags"}, // _, carry := arg0 + aux
- {name: "MaskIfNotCarry", argLength: 1, reg: crgp, asm: "ADDME", typ: "Int64"}, // carry - 1 (if carry then 0 else -1)
+ {name: "ADDconstForCarry", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, clobbers: tmp}, aux: "Int16", asm: "ADDC", typ: "Flags"}, // _, carry := arg0 + aux
+ {name: "MaskIfNotCarry", argLength: 1, reg: crgp, asm: "ADDME", typ: "Int64"}, // carry - 1 (if carry then 0 else -1)
{name: "SRADconst", argLength: 1, reg: gp11, asm: "SRAD", aux: "Int64"}, // arg0 >>a aux, 64 bits
{name: "SRAWconst", argLength: 1, reg: gp11, asm: "SRAW", aux: "Int64"}, // arg0 >>a aux, 32 bits
@@ -201,9 +201,9 @@ func init() {
{name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true}, // arg0^^arg1
{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0
- {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0|aux
- {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"}, // arg0^aux
- {name: "ANDconst", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}, clobbers: cr}, asm: "ANDCC", aux: "Int64"}, // arg0&aux // and-immediate sets CC on PPC, always.
+ {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0|aux
+ {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"}, // arg0^aux
+ {name: "ANDconst", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}, asm: "ANDCC", aux: "Int64", clobberFlags: true}, // arg0&aux // and-immediate sets CC on PPC, always.
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", typ: "Int64"}, // sign extend int8 to int64
{name: "MOVBZreg", argLength: 1, reg: gp11, asm: "MOVBZ", typ: "Int64"}, // zero extend uint8 to uint64
@@ -264,16 +264,16 @@ func init() {
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{ctxt}}},
//arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
- {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gp | sp | sb}, clobbers: cr | tmp}},
+ {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gp | sp | sb}, clobbers: tmp}, clobberFlags: true},
// Convert pointer to integer, takes a memory operand for ordering.
{name: "MOVDconvert", argLength: 2, reg: gp11, asm: "MOVD"},
- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
- {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gp | sp, ctxt, 0}, clobbers: callerSave}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
- {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+ {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
+ {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gp | sp, ctxt, 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+ {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
+ {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// large or unaligned zeroing
// arg0 = address of memory to zero (in R3, changed as side effect)
@@ -290,9 +290,10 @@ func init() {
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("R3"), gp},
- clobbers: buildReg("R3 CR"),
+ clobbers: buildReg("R3"),
},
- typ: "Mem",
+ clobberFlags: true,
+ typ: "Mem",
},
// large or unaligned move
@@ -313,9 +314,10 @@ func init() {
argLength: 4,
reg: regInfo{
inputs: []regMask{buildReg("R3"), buildReg("R4"), gp},
- clobbers: buildReg("R3 R4 CR"),
+ clobbers: buildReg("R3 R4"),
},
- typ: "Mem",
+ clobberFlags: true,
+ typ: "Mem",
},
// (InvertFlags (CMP a b)) == (CMP b a)
@@ -362,7 +364,6 @@ func init() {
regnames: regNamesPPC64,
gpregmask: gp,
fpregmask: fp,
- flagmask: cr,
framepointerreg: int8(num["SP"]),
})
}
diff --git a/src/cmd/compile/internal/ssa/gen/main.go b/src/cmd/compile/internal/ssa/gen/main.go
index 19e83a6216..19c1bc7163 100644
--- a/src/cmd/compile/internal/ssa/gen/main.go
+++ b/src/cmd/compile/internal/ssa/gen/main.go
@@ -29,7 +29,6 @@ type arch struct {
regnames []string
gpregmask regMask
fpregmask regMask
- flagmask regMask
framepointerreg int8
generic bool
}
@@ -44,6 +43,7 @@ type opData struct {
argLength int32 // number of arguments, if -1, then this operation has a variable number of arguments
commutative bool // this operation is commutative on its first 2 arguments (e.g. addition)
resultInArg0 bool // last output of v and v.Args[0] must be allocated to the same register
+ clobberFlags bool // this op clobbers flags register
}
type blockData struct {
@@ -167,6 +167,9 @@ func genOp() {
log.Fatalf("input[1] and last output register must be equal for %s", v.name)
}
}
+ if v.clobberFlags {
+ fmt.Fprintln(w, "clobberFlags: true,")
+ }
if a.name == "generic" {
fmt.Fprintln(w, "generic:true,")
fmt.Fprintln(w, "},") // close op
@@ -204,9 +207,7 @@ func genOp() {
// reg outputs
s = s[:0]
for i, r := range v.reg.outputs {
- if r != 0 {
- s = append(s, intPair{countRegs(r), i})
- }
+ s = append(s, intPair{countRegs(r), i})
}
if len(s) > 0 {
sort.Sort(byKey(s))
@@ -240,7 +241,6 @@ func genOp() {
fmt.Fprintln(w, "}")
fmt.Fprintf(w, "var gpRegMask%s = regMask(%d)\n", a.name, a.gpregmask)
fmt.Fprintf(w, "var fpRegMask%s = regMask(%d)\n", a.name, a.fpregmask)
- fmt.Fprintf(w, "var flagRegMask%s = regMask(%d)\n", a.name, a.flagmask)
fmt.Fprintf(w, "var framepointerReg%s = int8(%d)\n", a.name, a.framepointerreg)
}
diff --git a/src/cmd/compile/internal/ssa/op.go b/src/cmd/compile/internal/ssa/op.go
index c7a66c34ef..987cbd7b56 100644
--- a/src/cmd/compile/internal/ssa/op.go
+++ b/src/cmd/compile/internal/ssa/op.go
@@ -27,6 +27,7 @@ type opInfo struct {
rematerializeable bool // this op is rematerializeable
commutative bool // this operation is commutative (e.g. addition)
resultInArg0 bool // last output of v and v.Args[0] must be allocated to the same register
+ clobberFlags bool // this op clobbers flags register
}
type inputInfo struct {
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index b5225dd24d..68b60f2180 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1654,31 +1654,31 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "ADDL",
- argLen: 2,
- commutative: true,
- asm: x86.AADDL,
+ name: "ADDL",
+ argLen: 2,
+ commutative: true,
+ clobberFlags: true,
+ asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{1, 239}, // AX CX DX BX BP SI DI
{0, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "ADDLconst",
- auxType: auxInt32,
- argLen: 1,
- asm: x86.AADDL,
+ name: "ADDLconst",
+ auxType: auxInt32,
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -1696,8 +1696,8 @@ var opcodeTable = [...]opInfo{
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
- {0, 131072}, // FLAGS
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 0},
+ {1, 239}, // AX CX DX BX BP SI DI
},
},
},
@@ -1712,8 +1712,8 @@ var opcodeTable = [...]opInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
- {0, 131072}, // FLAGS
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 0},
+ {1, 239}, // AX CX DX BX BP SI DI
},
},
},
@@ -1722,12 +1722,12 @@ var opcodeTable = [...]opInfo{
argLen: 3,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AADCL,
reg: regInfo{
inputs: []inputInfo{
- {2, 131072}, // FLAGS
- {0, 239}, // AX CX DX BX BP SI DI
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
+ {1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -1739,11 +1739,11 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AADCL,
reg: regInfo{
inputs: []inputInfo{
- {1, 131072}, // FLAGS
- {0, 239}, // AX CX DX BX BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -1754,13 +1754,13 @@ var opcodeTable = [...]opInfo{
name: "SUBL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -1771,12 +1771,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -1793,8 +1793,8 @@ var opcodeTable = [...]opInfo{
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
- {0, 131072}, // FLAGS
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 0},
+ {1, 239}, // AX CX DX BX BP SI DI
},
},
},
@@ -1809,8 +1809,8 @@ var opcodeTable = [...]opInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
- {0, 131072}, // FLAGS
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 0},
+ {1, 239}, // AX CX DX BX BP SI DI
},
},
},
@@ -1818,12 +1818,12 @@ var opcodeTable = [...]opInfo{
name: "SBBL",
argLen: 3,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASBBL,
reg: regInfo{
inputs: []inputInfo{
- {2, 131072}, // FLAGS
- {0, 239}, // AX CX DX BX BP SI DI
- {1, 239}, // AX CX DX BX BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
+ {1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -1835,11 +1835,11 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASBBL,
reg: regInfo{
inputs: []inputInfo{
- {1, 131072}, // FLAGS
- {0, 239}, // AX CX DX BX BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -1851,13 +1851,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -1868,117 +1868,123 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "HMULL",
- argLen: 2,
- asm: x86.AIMULL,
+ name: "HMULL",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULLU",
- argLen: 2,
- asm: x86.AMULL,
+ name: "HMULLU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULW",
- argLen: 2,
- asm: x86.AIMULW,
+ name: "HMULW",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULB",
- argLen: 2,
- asm: x86.AIMULB,
+ name: "HMULB",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULWU",
- argLen: 2,
- asm: x86.AMULW,
+ name: "HMULWU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULBU",
- argLen: 2,
- asm: x86.AMULB,
+ name: "HMULBU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "MULLQU",
- argLen: 2,
- asm: x86.AMULL,
+ name: "MULLQU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 4}, // DX
{1, 1}, // AX
@@ -1986,120 +1992,128 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVL",
- argLen: 2,
- asm: x86.AIDIVL,
+ name: "DIVL",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131076, // DX FLAGS
+ clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
- name: "DIVW",
- argLen: 2,
- asm: x86.AIDIVW,
+ name: "DIVW",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131076, // DX FLAGS
+ clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
- name: "DIVLU",
- argLen: 2,
- asm: x86.ADIVL,
+ name: "DIVLU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131076, // DX FLAGS
+ clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
- name: "DIVWU",
- argLen: 2,
- asm: x86.ADIVW,
+ name: "DIVWU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131076, // DX FLAGS
+ clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
- name: "MODL",
- argLen: 2,
- asm: x86.AIDIVL,
+ name: "MODL",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "MODW",
- argLen: 2,
- asm: x86.AIDIVW,
+ name: "MODW",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "MODLU",
- argLen: 2,
- asm: x86.ADIVL,
+ name: "MODLU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "MODWU",
- argLen: 2,
- asm: x86.ADIVW,
+ name: "MODWU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
@@ -2110,13 +2124,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2127,12 +2141,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2143,13 +2157,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2160,12 +2174,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2176,13 +2190,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2193,12 +2207,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2213,9 +2227,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2227,9 +2238,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2241,9 +2249,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2255,9 +2260,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2269,9 +2271,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2283,9 +2282,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2297,9 +2293,6 @@ var opcodeTable = [...]opInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2311,9 +2304,6 @@ var opcodeTable = [...]opInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2325,9 +2315,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2339,9 +2326,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2353,9 +2337,6 @@ var opcodeTable = [...]opInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2367,9 +2348,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2381,9 +2359,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
@@ -2395,22 +2370,19 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- outputs: []outputInfo{
- {0, 131072}, // FLAGS
- },
},
},
{
name: "SHLL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2421,12 +2393,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2436,13 +2408,13 @@ var opcodeTable = [...]opInfo{
name: "SHRL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2452,13 +2424,13 @@ var opcodeTable = [...]opInfo{
name: "SHRW",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2468,13 +2440,13 @@ var opcodeTable = [...]opInfo{
name: "SHRB",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2485,12 +2457,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2501,12 +2473,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2517,12 +2489,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2532,13 +2504,13 @@ var opcodeTable = [...]opInfo{
name: "SARL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2548,13 +2520,13 @@ var opcodeTable = [...]opInfo{
name: "SARW",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2564,13 +2536,13 @@ var opcodeTable = [...]opInfo{
name: "SARB",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2581,12 +2553,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2597,12 +2569,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2613,12 +2585,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2629,12 +2601,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2645,12 +2617,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2661,12 +2633,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2676,12 +2648,12 @@ var opcodeTable = [...]opInfo{
name: "NEGL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANEGL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2691,68 +2663,68 @@ var opcodeTable = [...]opInfo{
name: "NOTL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANOTL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "BSFL",
- argLen: 1,
- asm: x86.ABSFL,
+ name: "BSFL",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSFL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "BSFW",
- argLen: 1,
- asm: x86.ABSFW,
+ name: "BSFW",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSFW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "BSRL",
- argLen: 1,
- asm: x86.ABSRL,
+ name: "BSRL",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSRL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "BSRW",
- argLen: 1,
- asm: x86.ABSRW,
+ name: "BSRW",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSRW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2762,12 +2734,12 @@ var opcodeTable = [...]opInfo{
name: "BSWAPL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ABSWAPL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 131072, // FLAGS
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2791,9 +2763,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASBBL,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2804,9 +2773,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETEQ,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2817,9 +2783,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETNE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2830,9 +2793,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLT,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2843,9 +2803,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2856,9 +2813,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETGT,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2869,9 +2823,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETGE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2882,9 +2833,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2895,9 +2843,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2908,9 +2853,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2921,37 +2863,30 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
- name: "SETEQF",
- argLen: 1,
- asm: x86.ASETEQ,
+ name: "SETEQF",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ASETEQ,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 238}, // CX DX BX BP SI DI
},
},
},
{
- name: "SETNEF",
- argLen: 1,
- asm: x86.ASETNE,
+ name: "SETNEF",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ASETNE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
- clobbers: 131073, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 238}, // CX DX BX BP SI DI
},
@@ -2962,9 +2897,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETPC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2975,9 +2907,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETPS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -2988,9 +2917,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -3001,9 +2927,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 131072}, // FLAGS
- },
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
@@ -3015,7 +2938,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVBLSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 255}, // AX CX DX BX SP BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -3028,7 +2951,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
- {0, 255}, // AX CX DX BX SP BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -3041,7 +2964,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVWLSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 255}, // AX CX DX BX SP BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -3054,7 +2977,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
- {0, 255}, // AX CX DX BX SP BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -3585,7 +3508,7 @@ var opcodeTable = [...]opInfo{
{0, 128}, // DI
{1, 1}, // AX
},
- clobbers: 131200, // DI FLAGS
+ clobbers: 128, // DI
},
},
{
@@ -3601,62 +3524,68 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "CALLstatic",
- auxType: auxSymOff,
- argLen: 1,
+ name: "CALLstatic",
+ auxType: auxSymOff,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 196591, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 FLAGS
+ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
- name: "CALLclosure",
- auxType: auxInt64,
- argLen: 3,
+ name: "CALLclosure",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 4}, // DX
{0, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 196591, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 FLAGS
+ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
- name: "CALLdefer",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLdefer",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 196591, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 FLAGS
+ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
- name: "CALLgo",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLgo",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 196591, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 FLAGS
+ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
- name: "CALLinter",
- auxType: auxInt64,
- argLen: 2,
+ name: "CALLinter",
+ auxType: auxInt64,
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
- clobbers: 196591, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 FLAGS
+ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
- name: "DUFFCOPY",
- auxType: auxInt64,
- argLen: 3,
+ name: "DUFFCOPY",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 64}, // SI
},
- clobbers: 131266, // CX SI DI FLAGS
+ clobbers: 194, // CX SI DI
},
},
{
@@ -3695,13 +3624,13 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "LoweredNilCheck",
- argLen: 2,
+ name: "LoweredNilCheck",
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
- clobbers: 131072, // FLAGS
},
},
{
@@ -3710,7 +3639,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
- {0, 255}, // AX CX DX BX SP BP SI DI
+ {0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
@@ -4060,62 +3989,62 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "ADDQ",
- argLen: 2,
- commutative: true,
- asm: x86.AADDQ,
+ name: "ADDQ",
+ argLen: 2,
+ commutative: true,
+ clobberFlags: true,
+ asm: x86.AADDQ,
reg: regInfo{
inputs: []inputInfo{
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "ADDL",
- argLen: 2,
- commutative: true,
- asm: x86.AADDL,
+ name: "ADDL",
+ argLen: 2,
+ commutative: true,
+ clobberFlags: true,
+ asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "ADDQconst",
- auxType: auxInt64,
- argLen: 1,
- asm: x86.AADDQ,
+ name: "ADDQconst",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.AADDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "ADDLconst",
- auxType: auxInt32,
- argLen: 1,
- asm: x86.AADDL,
+ name: "ADDLconst",
+ auxType: auxInt32,
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4125,13 +4054,13 @@ var opcodeTable = [...]opInfo{
name: "SUBQ",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4141,13 +4070,13 @@ var opcodeTable = [...]opInfo{
name: "SUBL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4158,12 +4087,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4174,12 +4103,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4190,13 +4119,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4207,13 +4136,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4224,12 +4153,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4240,132 +4169,140 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "HMULQ",
- argLen: 2,
- asm: x86.AIMULQ,
+ name: "HMULQ",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULQ,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULL",
- argLen: 2,
- asm: x86.AIMULL,
+ name: "HMULL",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULW",
- argLen: 2,
- asm: x86.AIMULW,
+ name: "HMULW",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULB",
- argLen: 2,
- asm: x86.AIMULB,
+ name: "HMULB",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULQU",
- argLen: 2,
- asm: x86.AMULQ,
+ name: "HMULQU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULQ,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULLU",
- argLen: 2,
- asm: x86.AMULL,
+ name: "HMULLU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULWU",
- argLen: 2,
- asm: x86.AMULW,
+ name: "HMULWU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
- name: "HMULBU",
- argLen: 2,
- asm: x86.AMULB,
+ name: "HMULBU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
@@ -4376,27 +4313,27 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "DIVQ",
- argLen: 2,
- asm: x86.AIDIVQ,
+ name: "DIVQ",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4404,15 +4341,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVL",
- argLen: 2,
- asm: x86.AIDIVL,
+ name: "DIVL",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4420,15 +4357,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVW",
- argLen: 2,
- asm: x86.AIDIVW,
+ name: "DIVW",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.AIDIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4436,15 +4373,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVQU",
- argLen: 2,
- asm: x86.ADIVQ,
+ name: "DIVQU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4452,15 +4389,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVLU",
- argLen: 2,
- asm: x86.ADIVL,
+ name: "DIVLU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4468,15 +4405,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIVWU",
- argLen: 2,
- asm: x86.ADIVW,
+ name: "DIVWU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: x86.ADIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 1}, // AX
{1, 4}, // DX
@@ -4488,13 +4425,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4505,13 +4442,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4522,12 +4459,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4538,12 +4475,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4554,13 +4491,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4571,13 +4508,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4588,12 +4525,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4604,12 +4541,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4620,13 +4557,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4637,13 +4574,13 @@ var opcodeTable = [...]opInfo{
argLen: 2,
commutative: true,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4654,12 +4591,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4670,12 +4607,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4690,9 +4627,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4704,9 +4638,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4718,9 +4649,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4732,9 +4660,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4746,9 +4671,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4760,9 +4682,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4774,9 +4693,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4788,9 +4704,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4802,9 +4715,6 @@ var opcodeTable = [...]opInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4816,9 +4726,6 @@ var opcodeTable = [...]opInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4830,9 +4737,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4844,9 +4748,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4858,9 +4759,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4872,9 +4770,6 @@ var opcodeTable = [...]opInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4886,9 +4781,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4900,9 +4792,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4914,9 +4803,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
@@ -4928,22 +4814,19 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- outputs: []outputInfo{
- {0, 8589934592}, // FLAGS
- },
},
},
{
name: "SHLQ",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLQ,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4953,13 +4836,13 @@ var opcodeTable = [...]opInfo{
name: "SHLL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4970,12 +4853,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -4986,12 +4869,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5001,13 +4884,13 @@ var opcodeTable = [...]opInfo{
name: "SHRQ",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRQ,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5017,13 +4900,13 @@ var opcodeTable = [...]opInfo{
name: "SHRL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5033,13 +4916,13 @@ var opcodeTable = [...]opInfo{
name: "SHRW",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5049,13 +4932,13 @@ var opcodeTable = [...]opInfo{
name: "SHRB",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5066,12 +4949,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5082,12 +4965,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5098,12 +4981,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5114,12 +4997,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5129,13 +5012,13 @@ var opcodeTable = [...]opInfo{
name: "SARQ",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARQ,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5145,13 +5028,13 @@ var opcodeTable = [...]opInfo{
name: "SARL",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5161,13 +5044,13 @@ var opcodeTable = [...]opInfo{
name: "SARW",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5177,13 +5060,13 @@ var opcodeTable = [...]opInfo{
name: "SARB",
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5194,12 +5077,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5210,12 +5093,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5226,12 +5109,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5242,12 +5125,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5258,12 +5141,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5274,12 +5157,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5290,12 +5173,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLW,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5306,12 +5189,12 @@ var opcodeTable = [...]opInfo{
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.AROLB,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5321,12 +5204,12 @@ var opcodeTable = [...]opInfo{
name: "NEGQ",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANEGQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5336,12 +5219,12 @@ var opcodeTable = [...]opInfo{
name: "NEGL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANEGL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5351,12 +5234,12 @@ var opcodeTable = [...]opInfo{
name: "NOTQ",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANOTQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5366,96 +5249,96 @@ var opcodeTable = [...]opInfo{
name: "NOTL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ANOTL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSFQ",
- argLen: 1,
- asm: x86.ABSFQ,
+ name: "BSFQ",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSFQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSFL",
- argLen: 1,
- asm: x86.ABSFL,
+ name: "BSFL",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSFL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSFW",
- argLen: 1,
- asm: x86.ABSFW,
+ name: "BSFW",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSFW,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSRQ",
- argLen: 1,
- asm: x86.ABSRQ,
+ name: "BSRQ",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSRQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSRL",
- argLen: 1,
- asm: x86.ABSRL,
+ name: "BSRL",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSRL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "BSRW",
- argLen: 1,
- asm: x86.ABSRW,
+ name: "BSRW",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ABSRW,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5466,13 +5349,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVQEQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5483,13 +5366,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVLEQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5500,13 +5383,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVLEQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5517,13 +5400,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt64,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVQNE,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5534,13 +5417,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVLNE,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5551,13 +5434,13 @@ var opcodeTable = [...]opInfo{
auxType: auxInt16,
argLen: 2,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ACMOVLNE,
reg: regInfo{
inputs: []inputInfo{
- {1, 8589934592}, // FLAGS
- {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5567,12 +5450,12 @@ var opcodeTable = [...]opInfo{
name: "BSWAPQ",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ABSWAPQ,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5582,12 +5465,12 @@ var opcodeTable = [...]opInfo{
name: "BSWAPL",
argLen: 1,
resultInArg0: true,
+ clobberFlags: true,
asm: x86.ABSWAPL,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5611,9 +5494,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASBBQ,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5624,9 +5504,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASBBL,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5637,9 +5514,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETEQ,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5650,9 +5524,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETNE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5663,9 +5534,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLT,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5676,9 +5544,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5689,9 +5554,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETGT,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5702,9 +5564,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETGE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5715,9 +5574,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5728,9 +5584,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETLS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5741,9 +5594,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5754,37 +5604,30 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "SETEQF",
- argLen: 1,
- asm: x86.ASETEQ,
+ name: "SETEQF",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ASETEQ,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
},
},
{
- name: "SETNEF",
- argLen: 1,
- asm: x86.ASETNE,
+ name: "SETNEF",
+ argLen: 1,
+ clobberFlags: true,
+ asm: x86.ASETNE,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
- clobbers: 8589934593, // AX FLAGS
+ clobbers: 1, // AX
outputs: []outputInfo{
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5795,9 +5638,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETPC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5808,9 +5648,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETPS,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5821,9 +5658,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5834,9 +5668,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
- inputs: []inputInfo{
- {0, 8589934592}, // FLAGS
- },
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
@@ -5848,7 +5679,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVBQSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5861,7 +5692,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVBQZX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5874,7 +5705,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVWQSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5887,7 +5718,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVWQZX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5900,7 +5731,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVLQSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5913,7 +5744,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVLQZX,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -6657,15 +6488,16 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DUFFZERO",
- auxType: auxInt64,
- argLen: 3,
+ name: "DUFFZERO",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 65536}, // X0
},
- clobbers: 8589934720, // DI FLAGS
+ clobbers: 128, // DI
},
},
{
@@ -6692,62 +6524,68 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "CALLstatic",
- auxType: auxSymOff,
- argLen: 1,
+ name: "CALLstatic",
+ auxType: auxSymOff,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
+ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
{
- name: "CALLclosure",
- auxType: auxInt64,
- argLen: 3,
+ name: "CALLclosure",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 4}, // DX
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
+ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
{
- name: "CALLdefer",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLdefer",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
+ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
{
- name: "CALLgo",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLgo",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
+ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
{
- name: "CALLinter",
- auxType: auxInt64,
- argLen: 2,
+ name: "CALLinter",
+ auxType: auxInt64,
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
+ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
{
- name: "DUFFCOPY",
- auxType: auxInt64,
- argLen: 3,
+ name: "DUFFCOPY",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 64}, // SI
},
- clobbers: 8590000320, // SI DI X0 FLAGS
+ clobbers: 65728, // SI DI X0
},
},
{
@@ -6786,13 +6624,13 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "LoweredNilCheck",
- argLen: 2,
+ name: "LoweredNilCheck",
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
- clobbers: 8589934592, // FLAGS
},
},
{
@@ -6801,7 +6639,7 @@ var opcodeTable = [...]opInfo{
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
},
outputs: []outputInfo{
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -6965,60 +6803,60 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "DIV",
- argLen: 2,
- asm: arm.ADIV,
+ name: "DIV",
+ argLen: 2,
+ clobberFlags: true,
+ asm: arm.ADIV,
reg: regInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- clobbers: 4294967296, // FLAGS
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
{
- name: "DIVU",
- argLen: 2,
- asm: arm.ADIVU,
+ name: "DIVU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: arm.ADIVU,
reg: regInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- clobbers: 4294967296, // FLAGS
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
{
- name: "MOD",
- argLen: 2,
- asm: arm.AMOD,
+ name: "MOD",
+ argLen: 2,
+ clobberFlags: true,
+ asm: arm.AMOD,
reg: regInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- clobbers: 4294967296, // FLAGS
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
{
- name: "MODU",
- argLen: 2,
- asm: arm.AMODU,
+ name: "MODU",
+ argLen: 2,
+ clobberFlags: true,
+ asm: arm.AMODU,
reg: regInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- clobbers: 4294967296, // FLAGS
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -7035,8 +6873,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -7050,8 +6888,8 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -7062,9 +6900,8 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7078,8 +6915,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {1, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7096,8 +6932,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -7111,8 +6947,8 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -7126,8 +6962,8 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -7137,9 +6973,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7153,8 +6988,7 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {1, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7168,8 +7002,7 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {1, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7555,7 +7388,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- clobbers: 4294967296, // FLAGS
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -7952,9 +7784,8 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7968,9 +7799,8 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -7984,9 +7814,8 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8000,9 +7829,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8016,9 +7844,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8032,9 +7859,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8048,9 +7874,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8064,9 +7889,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8080,9 +7904,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8100,8 +7923,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8116,8 +7939,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8132,8 +7955,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8148,8 +7971,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8164,8 +7987,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8180,8 +8003,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8196,8 +8019,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8212,8 +8035,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8228,8 +8051,8 @@ var opcodeTable = [...]opInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8596,10 +8419,9 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8612,10 +8434,9 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8628,10 +8449,9 @@ var opcodeTable = [...]opInfo{
asm: arm.AADC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8644,10 +8464,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8660,10 +8479,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8676,10 +8494,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ASBC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8692,10 +8509,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8708,10 +8524,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8724,10 +8539,9 @@ var opcodeTable = [...]opInfo{
asm: arm.ARSC,
reg: regInfo{
inputs: []inputInfo{
- {3, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -8745,8 +8559,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8761,8 +8575,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8777,8 +8591,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8793,8 +8607,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8809,8 +8623,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8825,8 +8639,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8841,8 +8655,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8857,8 +8671,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8873,8 +8687,8 @@ var opcodeTable = [...]opInfo{
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 0},
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
},
},
@@ -8887,9 +8701,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8901,9 +8712,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8915,9 +8723,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8929,9 +8734,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8944,9 +8746,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8958,9 +8757,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8973,9 +8769,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -8987,9 +8780,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9001,9 +8791,6 @@ var opcodeTable = [...]opInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9015,9 +8802,6 @@ var opcodeTable = [...]opInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9030,9 +8814,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9045,9 +8826,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9060,9 +8838,6 @@ var opcodeTable = [...]opInfo{
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9075,9 +8850,6 @@ var opcodeTable = [...]opInfo{
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9090,9 +8862,6 @@ var opcodeTable = [...]opInfo{
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9105,9 +8874,6 @@ var opcodeTable = [...]opInfo{
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9118,9 +8884,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9131,9 +8894,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
- outputs: []outputInfo{
- {0, 4294967296}, // FLAGS
- },
},
},
{
@@ -9180,7 +8940,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589942784}, // SP SB
+ {0, 4294975488}, // SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9194,7 +8954,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9208,7 +8968,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVBU,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9222,7 +8982,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9236,7 +8996,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVHU,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9250,7 +9010,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9264,7 +9024,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVF,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -9278,7 +9038,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -9293,7 +9053,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9305,7 +9065,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9317,7 +9077,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9328,7 +9088,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVF,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
@@ -9340,7 +9100,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
@@ -9352,7 +9112,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9367,7 +9127,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9382,7 +9142,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9397,7 +9157,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9412,7 +9172,7 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9425,7 +9185,7 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9438,7 +9198,7 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9451,7 +9211,7 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
{2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
- {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
+ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
},
},
},
@@ -9671,8 +9431,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {1, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9687,8 +9446,7 @@ var opcodeTable = [...]opInfo{
asm: arm.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {1, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9701,9 +9459,8 @@ var opcodeTable = [...]opInfo{
asm: arm.ASRA,
reg: regInfo{
inputs: []inputInfo{
- {2, 4294967296}, // FLAGS
- {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
- {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
+ {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
@@ -9711,50 +9468,55 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "CALLstatic",
- auxType: auxSymOff,
- argLen: 1,
+ name: "CALLstatic",
+ auxType: auxSymOff,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
+ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
{
- name: "CALLclosure",
- auxType: auxInt64,
- argLen: 3,
+ name: "CALLclosure",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 128}, // R7
{0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
},
- clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
+ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
{
- name: "CALLdefer",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLdefer",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
+ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
{
- name: "CALLgo",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLgo",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
+ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
{
- name: "CALLinter",
- auxType: auxInt64,
- argLen: 2,
+ name: "CALLinter",
+ auxType: auxInt64,
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
+ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
},
},
{
@@ -9770,9 +9532,6 @@ var opcodeTable = [...]opInfo{
name: "Equal",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9782,9 +9541,6 @@ var opcodeTable = [...]opInfo{
name: "NotEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9794,9 +9550,6 @@ var opcodeTable = [...]opInfo{
name: "LessThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9806,9 +9559,6 @@ var opcodeTable = [...]opInfo{
name: "LessEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9818,9 +9568,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9830,9 +9577,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9842,9 +9586,6 @@ var opcodeTable = [...]opInfo{
name: "LessThanU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9854,9 +9595,6 @@ var opcodeTable = [...]opInfo{
name: "LessEqualU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9866,9 +9604,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterThanU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9878,9 +9613,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterEqualU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4294967296}, // FLAGS
- },
outputs: []outputInfo{
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
@@ -9911,29 +9643,31 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "LoweredZero",
- auxType: auxInt64,
- argLen: 4,
+ name: "LoweredZero",
+ auxType: auxInt64,
+ argLen: 4,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 2}, // R1
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- clobbers: 4294967298, // R1 FLAGS
+ clobbers: 2, // R1
},
},
{
- name: "LoweredMove",
- auxType: auxInt64,
- argLen: 4,
+ name: "LoweredMove",
+ auxType: auxInt64,
+ argLen: 4,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 4}, // R2
{1, 2}, // R1
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
},
- clobbers: 4294967302, // R1 R2 FLAGS
+ clobbers: 6, // R1 R2
},
},
{
@@ -10665,9 +10399,6 @@ var opcodeTable = [...]opInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10679,9 +10410,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10693,9 +10421,6 @@ var opcodeTable = [...]opInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10707,9 +10432,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10721,9 +10443,6 @@ var opcodeTable = [...]opInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10735,9 +10454,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10749,9 +10465,6 @@ var opcodeTable = [...]opInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10763,9 +10476,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10777,9 +10487,6 @@ var opcodeTable = [...]opInfo{
{0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
{1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10791,9 +10498,6 @@ var opcodeTable = [...]opInfo{
{0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
{1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
- outputs: []outputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
},
},
{
@@ -10840,7 +10544,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037391646720}, // SP SB
+ {0, 4611686018964258816}, // SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10854,7 +10558,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10868,7 +10572,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVBU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10882,7 +10586,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10896,7 +10600,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVHU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10910,7 +10614,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10924,7 +10628,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVWU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10938,7 +10642,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -10952,7 +10656,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AFMOVS,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
@@ -10966,7 +10670,7 @@ var opcodeTable = [...]opInfo{
asm: arm64.AFMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
outputs: []outputInfo{
{0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
@@ -10981,7 +10685,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -10993,7 +10697,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -11005,7 +10709,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -11017,7 +10721,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -11029,7 +10733,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -11041,7 +10745,7 @@ var opcodeTable = [...]opInfo{
reg: regInfo{
inputs: []inputInfo{
{1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
- {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
+ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
},
},
},
@@ -11376,9 +11080,8 @@ var opcodeTable = [...]opInfo{
asm: arm64.ACSEL,
reg: regInfo{
inputs: []inputInfo{
- {2, 4611686018427387904}, // FLAGS
- {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
- {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
+ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
+ {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
@@ -11386,50 +11089,55 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "CALLstatic",
- auxType: auxSymOff,
- argLen: 1,
+ name: "CALLstatic",
+ auxType: auxSymOff,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS
+ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
},
{
- name: "CALLclosure",
- auxType: auxInt64,
- argLen: 3,
+ name: "CALLclosure",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 67108864}, // R26
{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 SP
},
- clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS
+ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
},
{
- name: "CALLdefer",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLdefer",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS
+ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
},
{
- name: "CALLgo",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLgo",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS
+ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
},
{
- name: "CALLinter",
- auxType: auxInt64,
- argLen: 2,
+ name: "CALLinter",
+ auxType: auxInt64,
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
- clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS
+ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
},
},
{
@@ -11445,9 +11153,6 @@ var opcodeTable = [...]opInfo{
name: "Equal",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11457,9 +11162,6 @@ var opcodeTable = [...]opInfo{
name: "NotEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11469,9 +11171,6 @@ var opcodeTable = [...]opInfo{
name: "LessThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11481,9 +11180,6 @@ var opcodeTable = [...]opInfo{
name: "LessEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11493,9 +11189,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11505,9 +11198,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11517,9 +11207,6 @@ var opcodeTable = [...]opInfo{
name: "LessThanU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11529,9 +11216,6 @@ var opcodeTable = [...]opInfo{
name: "LessEqualU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11541,9 +11225,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterThanU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11553,9 +11234,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterEqualU",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 4611686018427387904}, // FLAGS
- },
outputs: []outputInfo{
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
@@ -11573,28 +11251,30 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "LoweredZero",
- auxType: auxInt64,
- argLen: 3,
+ name: "LoweredZero",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 65536}, // R16
{1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
- clobbers: 4611686018427453440, // R16 FLAGS
+ clobbers: 65536, // R16
},
},
{
- name: "LoweredMove",
- auxType: auxInt64,
- argLen: 4,
+ name: "LoweredMove",
+ auxType: auxInt64,
+ argLen: 4,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 131072}, // R17
{1, 65536}, // R16
{2, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
},
- clobbers: 4611686018427584512, // R16 R17 FLAGS
+ clobbers: 196608, // R16 R17
},
},
{
@@ -11965,9 +11645,6 @@ var opcodeTable = [...]opInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
clobbers: 1073741824, // R31
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -11975,9 +11652,6 @@ var opcodeTable = [...]opInfo{
argLen: 1,
asm: ppc64.AADDME,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12281,15 +11955,15 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "ANDconst",
- auxType: auxInt64,
- argLen: 1,
- asm: ppc64.AANDCC,
+ name: "ANDconst",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
+ asm: ppc64.AANDCC,
reg: regInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 9223372036854775808, // CR
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12685,9 +12359,6 @@ var opcodeTable = [...]opInfo{
{0, 9223372032559808512}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
{1, 9223372032559808512}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12699,9 +12370,6 @@ var opcodeTable = [...]opInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
{1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12713,9 +12381,6 @@ var opcodeTable = [...]opInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
{1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12727,9 +12392,6 @@ var opcodeTable = [...]opInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
{1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12741,9 +12403,6 @@ var opcodeTable = [...]opInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
{1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12755,9 +12414,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12769,9 +12425,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12783,9 +12436,6 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
@@ -12797,18 +12447,12 @@ var opcodeTable = [...]opInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- outputs: []outputInfo{
- {0, 9223372036854775808}, // CR
- },
},
},
{
name: "Equal",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12818,9 +12462,6 @@ var opcodeTable = [...]opInfo{
name: "NotEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12830,9 +12471,6 @@ var opcodeTable = [...]opInfo{
name: "LessThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12842,9 +12480,6 @@ var opcodeTable = [...]opInfo{
name: "LessEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12854,9 +12489,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterThan",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12866,9 +12498,6 @@ var opcodeTable = [...]opInfo{
name: "GreaterEqual",
argLen: 1,
reg: regInfo{
- inputs: []inputInfo{
- {0, 9223372036854775808}, // CR
- },
outputs: []outputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
@@ -12884,13 +12513,14 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "LoweredNilCheck",
- argLen: 2,
+ name: "LoweredNilCheck",
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 9223372037928517632, // R31 CR
+ clobbers: 1073741824, // R31
},
},
{
@@ -12907,75 +12537,82 @@ var opcodeTable = [...]opInfo{
},
},
{
- name: "CALLstatic",
- auxType: auxSymOff,
- argLen: 1,
+ name: "CALLstatic",
+ auxType: auxSymOff,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 18446744069951451132, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 CR
+ clobbers: 9223372033096675324, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
- name: "CALLclosure",
- auxType: auxInt64,
- argLen: 3,
+ name: "CALLclosure",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 1024}, // R11
{0, 536866813}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 18446744069951451132, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 CR
+ clobbers: 9223372033096675324, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
- name: "CALLdefer",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLdefer",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 18446744069951451132, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 CR
+ clobbers: 9223372033096675324, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
- name: "CALLgo",
- auxType: auxInt64,
- argLen: 1,
+ name: "CALLgo",
+ auxType: auxInt64,
+ argLen: 1,
+ clobberFlags: true,
reg: regInfo{
- clobbers: 18446744069951451132, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 CR
+ clobbers: 9223372033096675324, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
- name: "CALLinter",
- auxType: auxInt64,
- argLen: 2,
+ name: "CALLinter",
+ auxType: auxInt64,
+ argLen: 2,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 18446744069951451132, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 CR
+ clobbers: 9223372033096675324, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
- name: "LoweredZero",
- auxType: auxInt64,
- argLen: 3,
+ name: "LoweredZero",
+ auxType: auxInt64,
+ argLen: 3,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 4}, // R3
{1, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 9223372036854775812, // R3 CR
+ clobbers: 4, // R3
},
},
{
- name: "LoweredMove",
- auxType: auxInt64,
- argLen: 4,
+ name: "LoweredMove",
+ auxType: auxInt64,
+ argLen: 4,
+ clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 4}, // R3
{1, 8}, // R4
{2, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
- clobbers: 9223372036854775820, // R3 R4 CR
+ clobbers: 12, // R3 R4
},
},
{
@@ -14594,11 +14231,9 @@ var registers386 = [...]Register{
{14, "X6"},
{15, "X7"},
{16, "SB"},
- {17, "FLAGS"},
}
var gpRegMask386 = regMask(239)
var fpRegMask386 = regMask(65280)
-var flagRegMask386 = regMask(131072)
var framepointerReg386 = int8(5)
var registersAMD64 = [...]Register{
{0, "AX"},
@@ -14634,11 +14269,9 @@ var registersAMD64 = [...]Register{
{30, "X14"},
{31, "X15"},
{32, "SB"},
- {33, "FLAGS"},
}
var gpRegMaskAMD64 = regMask(65519)
var fpRegMaskAMD64 = regMask(4294901760)
-var flagRegMaskAMD64 = regMask(8589934592)
var framepointerRegAMD64 = int8(5)
var registersARM = [...]Register{
{0, "R0"},
@@ -14673,12 +14306,10 @@ var registersARM = [...]Register{
{29, "F13"},
{30, "F14"},
{31, "F15"},
- {32, "FLAGS"},
- {33, "SB"},
+ {32, "SB"},
}
var gpRegMaskARM = regMask(5119)
var fpRegMaskARM = regMask(4294901760)
-var flagRegMaskARM = regMask(4294967296)
var framepointerRegARM = int8(-1)
var registersARM64 = [...]Register{
{0, "R0"},
@@ -14743,12 +14374,10 @@ var registersARM64 = [...]Register{
{59, "F29"},
{60, "F30"},
{61, "F31"},
- {62, "FLAGS"},
- {63, "SB"},
+ {62, "SB"},
}
var gpRegMaskARM64 = regMask(133955583)
var fpRegMaskARM64 = regMask(288230375077969920)
-var flagRegMaskARM64 = regMask(4611686018427387904)
var framepointerRegARM64 = int8(-1)
var registersPPC64 = [...]Register{
{0, "SP"},
@@ -14814,9 +14443,7 @@ var registersPPC64 = [...]Register{
{60, "F29"},
{61, "F30"},
{62, "F31"},
- {63, "CR"},
}
var gpRegMaskPPC64 = regMask(536866812)
var fpRegMaskPPC64 = regMask(9223372032559808512)
-var flagRegMaskPPC64 = regMask(9223372036854775808)
var framepointerRegPPC64 = int8(0)
diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go
index de0d8b1a0e..493a370972 100644
--- a/src/cmd/compile/internal/ssa/regalloc.go
+++ b/src/cmd/compile/internal/ssa/regalloc.go
@@ -1060,10 +1060,6 @@ func (s *regAllocState) regalloc(f *Func) {
args = append(args[:0], v.Args...)
for _, i := range regspec.inputs {
mask := i.regs
- if mask == f.Config.flagRegMask {
- // TODO: remove flag input from regspec.inputs.
- continue
- }
if mask&s.values[args[i.idx].ID].regs == 0 {
// Need a new register for the input.
mask &= s.allocatable
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