[dev.power64] 5g,6g,8g,9g: debug prints for regopt pass 6 and paint2

Theses were very helpful in understanding the regions and
register selection when porting regopt to 9g.  Add them to the
other compilers (and improve 9g's successor debug print).

LGTM=rsc
R=rsc
CC=golang-codereviews
https://golang.org/cl/174130043

7 files changed, 94 insertions, 50 deletions

diff --git a/src/cmd/5g/opt.h b/src/cmd/5g/opt.h
index 01edeb84d8..a606f1d310 100644
--- a/src/cmd/5g/opt.h
+++ b/src/cmd/5g/opt.h
@@ -160,7 +160,7 @@ void	prop(Reg*, Bits, Bits);
 void	synch(Reg*, Bits);
 uint32	allreg(uint32, Rgn*);
 void	paint1(Reg*, int);
-uint32	paint2(Reg*, int);
+uint32	paint2(Reg*, int, int);
 void	paint3(Reg*, int, uint32, int);
 void	addreg(Adr*, int);
 void	dumpit(char *str, Flow *r0, int);
diff --git a/src/cmd/5g/reg.c b/src/cmd/5g/reg.c
index 712841329e..86a1f7efb1 100644
--- a/src/cmd/5g/reg.c
+++ b/src/cmd/5g/reg.c
@@ -454,9 +454,13 @@ brk:
 	 * replace code (paint3)
 	 */
 	rgp = region;
+	if(debug['R'] && debug['v'])
+		print("\nregisterizing\n");
 	for(i=0; i<nregion; i++) {
+		if(debug['R'] && debug['v'])
+			print("region %d: cost %d varno %d enter %d\n", i, rgp->cost, rgp->varno, rgp->enter->f.prog->pc);
 		bit = blsh(rgp->varno);
-		vreg = paint2(rgp->enter, rgp->varno);
+		vreg = paint2(rgp->enter, rgp->varno, 0);
 		vreg = allreg(vreg, rgp);
 		if(debug['R']) {
 			if(rgp->regno >= NREG)
@@ -477,9 +481,6 @@ brk:
 		rgp++;
 	}
 
-	if(debug['R'] && debug['v'])
-		dumpit("pass6", &firstr->f, 1);
-
 	/*
 	 * free aux structures. peep allocates new ones.
 	 */
@@ -488,6 +489,15 @@ brk:
 	flowend(g);
 	firstr = R;
 
+	if(debug['R'] && debug['v']) {
+		// Rebuild flow graph, since we inserted instructions
+		g = flowstart(firstp, sizeof(Reg));
+		firstr = (Reg*)g->start;
+		dumpit("pass6", &firstr->f, 1);
+		flowend(g);
+		firstr = R;
+	}
+
 	/*
 	 * pass 7
 	 * peep-hole on basic block
@@ -1189,7 +1199,7 @@ paint1(Reg *r, int bn)
 }
 
 uint32
-paint2(Reg *r, int bn)
+paint2(Reg *r, int bn, int depth)
 {
 	Reg *r1;
 	int z;
@@ -1213,6 +1223,9 @@ paint2(Reg *r, int bn)
 		r = r1;
 	}
 	for(;;) {
+		if(debug['R'] && debug['v'])
+			print("  paint2 %d %P\n", depth, r->f.prog);
+
 		r->act.b[z] &= ~bb;
 
 		vreg |= r->regu;
@@ -1220,14 +1233,14 @@ paint2(Reg *r, int bn)
 		if(r->refbehind.b[z] & bb)
 			for(r1 = (Reg*)r->f.p2; r1 != R; r1 = (Reg*)r1->f.p2link)
 				if(r1->refahead.b[z] & bb)
-					vreg |= paint2(r1, bn);
+					vreg |= paint2(r1, bn, depth+1);
 
 		if(!(r->refahead.b[z] & bb))
 			break;
 		r1 = (Reg*)r->f.s2;
 		if(r1 != R)
 			if(r1->refbehind.b[z] & bb)
-				vreg |= paint2(r1, bn);
+				vreg |= paint2(r1, bn, depth+1);
 		r = (Reg*)r->f.s1;
 		if(r == R)
 			break;
@@ -1344,6 +1357,8 @@ RtoB(int r)
 int
 BtoR(uint32 b)
 {
+	// TODO Allow R0 and R1, but be careful with a 0 return
+	// TODO Allow R9. Only R10 is reserved now (just g, not m).
 	b &= 0x11fcL;	// excluded R9 and R10 for m and g, but not R12
 	if(b == 0)
 		return 0;
@@ -1442,12 +1457,14 @@ dumpit(char *str, Flow *r0, int isreg)
 				print(" (only)");
 			print("\n");
 		}
-//		r1 = r->s1;
-//		if(r1 != nil) {
-//			print("	succ:");
-//			for(; r1 != R; r1 = r1->s1)
-//				print(" %.4ud", (int)r1->prog->pc);
-//			print("\n");
-//		}
+		// Print successors if it's not just the next one
+		if(r->s1 != r->link || r->s2 != nil) {
+			print("	succ:");
+			if(r->s1 != nil)
+				print(" %.4ud", (int)r->s1->prog->pc);
+			if(r->s2 != nil)
+				print(" %.4ud", (int)r->s2->prog->pc);
+			print("\n");
+		}
 	}
 }
diff --git a/src/cmd/6g/opt.h b/src/cmd/6g/opt.h
index 08486a04a0..493171ef82 100644
--- a/src/cmd/6g/opt.h
+++ b/src/cmd/6g/opt.h
@@ -156,7 +156,7 @@ void	prop(Reg*, Bits, Bits);
 void	synch(Reg*, Bits);
 uint32	allreg(uint32, Rgn*);
 void	paint1(Reg*, int);
-uint32	paint2(Reg*, int);
+uint32	paint2(Reg*, int, int);
 void	paint3(Reg*, int, uint32, int);
 void	addreg(Adr*, int);
 void	dumpone(Flow*, int);
diff --git a/src/cmd/6g/reg.c b/src/cmd/6g/reg.c
index 4ce2f4db00..75f9573b2e 100644
--- a/src/cmd/6g/reg.c
+++ b/src/cmd/6g/reg.c
@@ -389,9 +389,13 @@ brk:
 	 * replace code (paint3)
 	 */
 	rgp = region;
+	if(debug['R'] && debug['v'])
+		print("\nregisterizing\n");
 	for(i=0; i<nregion; i++) {
+		if(debug['R'] && debug['v'])
+			print("region %d: cost %d varno %d enter %d\n", i, rgp->cost, rgp->varno, rgp->enter->f.prog->pc);
 		bit = blsh(rgp->varno);
-		vreg = paint2(rgp->enter, rgp->varno);
+		vreg = paint2(rgp->enter, rgp->varno, 0);
 		vreg = allreg(vreg, rgp);
 		if(rgp->regno != 0) {
 			if(debug['R'] && debug['v']) {
@@ -406,9 +410,6 @@ brk:
 		rgp++;
 	}
 
-	if(debug['R'] && debug['v'])
-		dumpit("pass6", &firstr->f, 1);
-	
 	/*
 	 * free aux structures. peep allocates new ones.
 	 */
@@ -417,6 +418,15 @@ brk:
 	flowend(g);
 	firstr = R;
 
+	if(debug['R'] && debug['v']) {
+		// Rebuild flow graph, since we inserted instructions
+		g = flowstart(firstp, sizeof(Reg));
+		firstr = (Reg*)g->start;
+		dumpit("pass6", &firstr->f, 1);
+		flowend(g);
+		firstr = R;
+	}
+
 	/*
 	 * pass 7
 	 * peep-hole on basic block
@@ -1020,7 +1030,7 @@ paint1(Reg *r, int bn)
 }
 
 uint32
-paint2(Reg *r, int bn)
+paint2(Reg *r, int bn, int depth)
 {
 	Reg *r1;
 	int z;
@@ -1044,6 +1054,9 @@ paint2(Reg *r, int bn)
 		r = r1;
 	}
 	for(;;) {
+		if(debug['R'] && debug['v'])
+			print("  paint2 %d %P\n", depth, r->f.prog);
+
 		r->act.b[z] &= ~bb;
 
 		vreg |= r->regu;
@@ -1051,14 +1064,14 @@ paint2(Reg *r, int bn)
 		if(r->refbehind.b[z] & bb)
 			for(r1 = (Reg*)r->f.p2; r1 != R; r1 = (Reg*)r1->f.p2link)
 				if(r1->refahead.b[z] & bb)
-					vreg |= paint2(r1, bn);
+					vreg |= paint2(r1, bn, depth+1);
 
 		if(!(r->refahead.b[z] & bb))
 			break;
 		r1 = (Reg*)r->f.s2;
 		if(r1 != R)
 			if(r1->refbehind.b[z] & bb)
-				vreg |= paint2(r1, bn);
+				vreg |= paint2(r1, bn, depth+1);
 		r = (Reg*)r->f.s1;
 		if(r == R)
 			break;
@@ -1259,12 +1272,14 @@ dumpit(char *str, Flow *r0, int isreg)
 				print(" %.4ud", (int)r1->prog->pc);
 			print("\n");
 		}
-//		r1 = r->s1;
-//		if(r1 != R) {
-//			print("	succ:");
-//			for(; r1 != R; r1 = r1->s1)
-//				print(" %.4ud", (int)r1->prog->pc);
-//			print("\n");
-//		}
+		// Print successors if it's not just the next one
+		if(r->s1 != r->link || r->s2 != nil) {
+			print("	succ:");
+			if(r->s1 != nil)
+				print(" %.4ud", (int)r->s1->prog->pc);
+			if(r->s2 != nil)
+				print(" %.4ud", (int)r->s2->prog->pc);
+			print("\n");
+		}
 	}
 }
diff --git a/src/cmd/8g/opt.h b/src/cmd/8g/opt.h
index 11ee66e081..5445f91275 100644
--- a/src/cmd/8g/opt.h
+++ b/src/cmd/8g/opt.h
@@ -174,7 +174,7 @@ void	loopit(Reg*, int32);
 void	synch(Reg*, Bits);
 uint32	allreg(uint32, Rgn*);
 void	paint1(Reg*, int);
-uint32	paint2(Reg*, int);
+uint32	paint2(Reg*, int, int);
 void	paint3(Reg*, int, uint32, int);
 void	addreg(Adr*, int);
 void	dumpone(Flow*, int);
diff --git a/src/cmd/8g/reg.c b/src/cmd/8g/reg.c
index 79d60bed55..45aea2c337 100644
--- a/src/cmd/8g/reg.c
+++ b/src/cmd/8g/reg.c
@@ -358,18 +358,19 @@ brk:
 	 * replace code (paint3)
 	 */
 	rgp = region;
+	if(debug['R'] && debug['v'])
+		print("\nregisterizing\n");
 	for(i=0; i<nregion; i++) {
+		if(debug['R'] && debug['v'])
+			print("region %d: cost %d varno %d enter %d\n", i, rgp->cost, rgp->varno, rgp->enter->f.prog->pc);
 		bit = blsh(rgp->varno);
-		vreg = paint2(rgp->enter, rgp->varno);
+		vreg = paint2(rgp->enter, rgp->varno, 0);
 		vreg = allreg(vreg, rgp);
 		if(rgp->regno != 0)
 			paint3(rgp->enter, rgp->varno, vreg, rgp->regno);
 		rgp++;
 	}
 
-	if(debug['R'] && debug['v'])
-		dumpit("pass6", &firstr->f, 1);
-
 	/*
 	 * free aux structures. peep allocates new ones.
 	 */
@@ -378,6 +379,15 @@ brk:
 	flowend(g);
 	firstr = R;
 
+	if(debug['R'] && debug['v']) {
+		// Rebuild flow graph, since we inserted instructions
+		g = flowstart(firstp, sizeof(Reg));
+		firstr = (Reg*)g->start;
+		dumpit("pass6", &firstr->f, 1);
+		flowend(g);
+		firstr = R;
+	}
+
 	/*
 	 * pass 7
 	 * peep-hole on basic block
@@ -996,7 +1006,7 @@ paint1(Reg *r, int bn)
 }
 
 uint32
-paint2(Reg *r, int bn)
+paint2(Reg *r, int bn, int depth)
 {
 	Reg *r1;
 	int z;
@@ -1020,6 +1030,9 @@ paint2(Reg *r, int bn)
 		r = r1;
 	}
 	for(;;) {
+		if(debug['R'] && debug['v'])
+			print("  paint2 %d %P\n", depth, r->f.prog);
+
 		r->act.b[z] &= ~bb;
 
 		vreg |= r->regu;
@@ -1027,14 +1040,14 @@ paint2(Reg *r, int bn)
 		if(r->refbehind.b[z] & bb)
 			for(r1 = (Reg*)r->f.p2; r1 != R; r1 = (Reg*)r1->f.p2link)
 				if(r1->refahead.b[z] & bb)
-					vreg |= paint2(r1, bn);
+					vreg |= paint2(r1, bn, depth+1);
 
 		if(!(r->refahead.b[z] & bb))
 			break;
 		r1 = (Reg*)r->f.s2;
 		if(r1 != R)
 			if(r1->refbehind.b[z] & bb)
-				vreg |= paint2(r1, bn);
+				vreg |= paint2(r1, bn, depth+1);
 		r = (Reg*)r->f.s1;
 		if(r == R)
 			break;
@@ -1227,12 +1240,14 @@ dumpit(char *str, Flow *r0, int isreg)
 				print(" %.4ud", (int)r1->prog->pc);
 			print("\n");
 		}
-//		r1 = r->s1;
-//		if(r1 != nil) {
-//			print("	succ:");
-//			for(; r1 != R; r1 = r1->s1)
-//				print(" %.4ud", (int)r1->prog->pc);
-//			print("\n");
-//		}
+		// Print successors if it's not just the next one
+		if(r->s1 != r->link || r->s2 != nil) {
+			print("	succ:");
+			if(r->s1 != nil)
+				print(" %.4ud", (int)r->s1->prog->pc);
+			if(r->s2 != nil)
+				print(" %.4ud", (int)r->s2->prog->pc);
+			print("\n");
+		}
 	}
 }
diff --git a/src/cmd/9g/reg.c b/src/cmd/9g/reg.c
index b911a23998..2e546a95bb 100644
--- a/src/cmd/9g/reg.c
+++ b/src/cmd/9g/reg.c
@@ -1322,7 +1322,6 @@ void
 dumpit(char *str, Flow *r0, int isreg)
 {
 	Flow *r, *r1;
-	int s1v, s2v;
 
 	print("\n%s\n", str);
 	for(r = r0; r != nil; r = r->link) {
@@ -1334,10 +1333,8 @@ dumpit(char *str, Flow *r0, int isreg)
 				print(" %.4ud", (int)r1->prog->pc);
 			print("\n");
 		}
-		// If at least one successor is "interesting", print both
-		s1v = (r->s1 != nil) && (r->s1->prog != r->prog->link);
-		s2v = (r->s2 != nil) && (r->s2->prog != r->prog->link);
-		if(s1v || s2v) {
+		// Print successors if it's not just the next one
+		if(r->s1 != r->link || r->s2 != nil) {
 			print("	succ:");
 			if(r->s1 != nil)
 				print(" %.4ud", (int)r->s1->prog->pc);