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| author | Joel Sing <joel@sing.id.au> | 2021-07-16 02:56:08 +1000 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2021-09-17 18:33:15 +0000 |
| commit | 70493b3eb06d10217d9aa346ffff0b4c4f2cc72b (patch) | |
| tree | 6d35f7521a7824b3c8650193aa9f9f5a4a3c0d04 | |
| parent | 6d02ce85840fb7a1a9239d02e02710a008b1657a (diff) | |
| download | go-70493b3eb06d10217d9aa346ffff0b4c4f2cc72b.tar.gz go-70493b3eb06d10217d9aa346ffff0b4c4f2cc72b.zip | |
runtime/cgo: save and restore X3 (aka GP) for crosscall1 on riscv64
The C code that is calling crosscall1 may depend on the GP register, which Go code
will currently clobber. Save and restore both X3 (aka GP) and X4 (aka TP) in this
code path (note that the Go code does not currently clobber X4, however there is
minimal downside to saving and restoring it here, which then also matches crosscall2).
Updates #47100
Change-Id: Icbb706d7889d5dc59de3efb2b510fa6ea2069496
Reviewed-on: https://go-review.googlesource.com/c/go/+/334870
Trust: Joel Sing <joel@sing.id.au>
Trust: Meng Zhuo <mzh@golangcn.org>
Reviewed-by: Meng Zhuo <mzh@golangcn.org>
Reviewed-by: Ian Lance Taylor <iant@golang.org>
Run-TryBot: Meng Zhuo <mzh@golangcn.org>
| -rw-r--r-- | src/runtime/cgo/gcc_riscv64.S | 108 |
1 files changed, 56 insertions, 52 deletions
diff --git a/src/runtime/cgo/gcc_riscv64.S b/src/runtime/cgo/gcc_riscv64.S index f429dc64ee..fdc77496d9 100644 --- a/src/runtime/cgo/gcc_riscv64.S +++ b/src/runtime/cgo/gcc_riscv64.S @@ -8,36 +8,38 @@ * Calling into the gc tool chain, where all registers are caller save. * Called from standard RISCV ELF psABI, where x8-x9, x18-x27, f8-f9 and * f18-f27 are callee-save, so they must be saved explicitly, along with - * x1 (LR). + * x1 (LR), x3 (GP) and x4 (TP). */ .globl crosscall1 crosscall1: - sd x1, -200(sp) - addi sp, sp, -200 - sd x8, 8(sp) - sd x9, 16(sp) - sd x18, 24(sp) - sd x19, 32(sp) - sd x20, 40(sp) - sd x21, 48(sp) - sd x22, 56(sp) - sd x23, 64(sp) - sd x24, 72(sp) - sd x25, 80(sp) - sd x26, 88(sp) - sd x27, 96(sp) - fsd f8, 104(sp) - fsd f9, 112(sp) - fsd f18, 120(sp) - fsd f19, 128(sp) - fsd f20, 136(sp) - fsd f21, 144(sp) - fsd f22, 152(sp) - fsd f23, 160(sp) - fsd f24, 168(sp) - fsd f25, 176(sp) - fsd f26, 184(sp) - fsd f27, 192(sp) + sd x1, -216(sp) + addi sp, sp, -216 + sd x3, 8(sp) + sd x4, 16(sp) + sd x8, 24(sp) + sd x9, 32(sp) + sd x18, 40(sp) + sd x19, 48(sp) + sd x20, 56(sp) + sd x21, 64(sp) + sd x22, 72(sp) + sd x23, 80(sp) + sd x24, 88(sp) + sd x25, 96(sp) + sd x26, 104(sp) + sd x27, 112(sp) + fsd f8, 120(sp) + fsd f9, 128(sp) + fsd f18, 136(sp) + fsd f19, 144(sp) + fsd f20, 152(sp) + fsd f21, 160(sp) + fsd f22, 168(sp) + fsd f23, 176(sp) + fsd f24, 184(sp) + fsd f25, 192(sp) + fsd f26, 200(sp) + fsd f27, 208(sp) // a0 = *fn, a1 = *setg_gcc, a2 = *g mv s1, a0 @@ -47,31 +49,33 @@ crosscall1: jalr ra, s1 // call fn ld x1, 0(sp) - ld x8, 8(sp) - ld x9, 16(sp) - ld x18, 24(sp) - ld x19, 32(sp) - ld x20, 40(sp) - ld x21, 48(sp) - ld x22, 56(sp) - ld x23, 64(sp) - ld x24, 72(sp) - ld x25, 80(sp) - ld x26, 88(sp) - ld x27, 96(sp) - fld f8, 104(sp) - fld f9, 112(sp) - fld f18, 120(sp) - fld f19, 128(sp) - fld f20, 136(sp) - fld f21, 144(sp) - fld f22, 152(sp) - fld f23, 160(sp) - fld f24, 168(sp) - fld f25, 176(sp) - fld f26, 184(sp) - fld f27, 192(sp) - addi sp, sp, 200 + ld x3, 8(sp) + ld x4, 16(sp) + ld x8, 24(sp) + ld x9, 32(sp) + ld x18, 40(sp) + ld x19, 48(sp) + ld x20, 56(sp) + ld x21, 64(sp) + ld x22, 72(sp) + ld x23, 80(sp) + ld x24, 88(sp) + ld x25, 96(sp) + ld x26, 104(sp) + ld x27, 112(sp) + fld f8, 120(sp) + fld f9, 128(sp) + fld f18, 136(sp) + fld f19, 144(sp) + fld f20, 152(sp) + fld f21, 160(sp) + fld f22, 168(sp) + fld f23, 176(sp) + fld f24, 184(sp) + fld f25, 192(sp) + fld f26, 200(sp) + fld f27, 208(sp) + addi sp, sp, 216 jr ra |