// autogenerated: do not edit! // generated from gen/*Ops.go package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" "cmd/internal/obj/ppc64" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota Block386EQ Block386NE Block386LT Block386LE Block386GT Block386GE Block386ULT Block386ULE Block386UGT Block386UGE Block386EQF Block386NEF Block386ORD Block386NAN BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockARM64EQ BlockARM64NE BlockARM64LT BlockARM64LE BlockARM64GT BlockARM64GE BlockARM64ULT BlockARM64ULE BlockARM64UGT BlockARM64UGE BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64FLT BlockPPC64FLE BlockPPC64FGT BlockPPC64FGE BlockPlain BlockIf BlockCall BlockDefer BlockCheck BlockRet BlockRetJmp BlockExit BlockFirst ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", Block386EQ: "EQ", Block386NE: "NE", Block386LT: "LT", Block386LE: "LE", Block386GT: "GT", Block386GE: "GE", Block386ULT: "ULT", Block386ULE: "ULE", Block386UGT: "UGT", Block386UGE: "UGE", Block386EQF: "EQF", Block386NEF: "NEF", Block386ORD: "ORD", Block386NAN: "NAN", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockARM64EQ: "EQ", BlockARM64NE: "NE", BlockARM64LT: "LT", BlockARM64LE: "LE", BlockARM64GT: "GT", BlockARM64GE: "GE", BlockARM64ULT: "ULT", BlockARM64ULE: "ULE", BlockARM64UGT: "UGT", BlockARM64UGE: "UGE", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64FLT: "FLT", BlockPPC64FLE: "FLE", BlockPPC64FGT: "FGT", BlockPPC64FGE: "FGE", BlockPlain: "Plain", BlockIf: "If", BlockCall: "Call", BlockDefer: "Defer", BlockCheck: "Check", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockFirst: "First", } func (k BlockKind) String() string { return blockString[k] } const ( OpInvalid Op = iota Op386ADDSS Op386ADDSD Op386SUBSS Op386SUBSD Op386MULSS Op386MULSD Op386DIVSS Op386DIVSD Op386MOVSSload Op386MOVSDload Op386MOVSSconst Op386MOVSDconst Op386MOVSSloadidx1 Op386MOVSSloadidx4 Op386MOVSDloadidx1 Op386MOVSDloadidx8 Op386MOVSSstore Op386MOVSDstore Op386MOVSSstoreidx1 Op386MOVSSstoreidx4 Op386MOVSDstoreidx1 Op386MOVSDstoreidx8 Op386ADDL Op386ADDLconst Op386ADDLcarry Op386ADDLconstcarry Op386ADCL Op386ADCLconst Op386SUBL Op386SUBLconst Op386SUBLcarry Op386SUBLconstcarry Op386SBBL Op386SBBLconst Op386MULL Op386MULLconst Op386HMULL Op386HMULLU Op386HMULW Op386HMULB Op386HMULWU Op386HMULBU Op386MULLQU Op386DIVL Op386DIVW Op386DIVLU Op386DIVWU Op386MODL Op386MODW Op386MODLU Op386MODWU Op386ANDL Op386ANDLconst Op386ORL Op386ORLconst Op386XORL Op386XORLconst Op386CMPL Op386CMPW Op386CMPB Op386CMPLconst Op386CMPWconst Op386CMPBconst Op386UCOMISS Op386UCOMISD Op386TESTL Op386TESTW Op386TESTB Op386TESTLconst Op386TESTWconst Op386TESTBconst Op386SHLL Op386SHLLconst Op386SHRL Op386SHRW Op386SHRB Op386SHRLconst Op386SHRWconst Op386SHRBconst Op386SARL Op386SARW Op386SARB Op386SARLconst Op386SARWconst Op386SARBconst Op386ROLLconst Op386ROLWconst Op386ROLBconst Op386NEGL Op386NOTL Op386BSFL Op386BSFW Op386BSRL Op386BSRW Op386BSWAPL Op386SQRTSD Op386SBBLcarrymask Op386SETEQ Op386SETNE Op386SETL Op386SETLE Op386SETG Op386SETGE Op386SETB Op386SETBE Op386SETA Op386SETAE Op386SETEQF Op386SETNEF Op386SETORD Op386SETNAN Op386SETGF Op386SETGEF Op386MOVBLSX Op386MOVBLZX Op386MOVWLSX Op386MOVWLZX Op386MOVLconst Op386CVTTSD2SL Op386CVTTSS2SL Op386CVTSL2SS Op386CVTSL2SD Op386CVTSD2SS Op386CVTSS2SD Op386PXOR Op386LEAL Op386LEAL1 Op386LEAL2 Op386LEAL4 Op386LEAL8 Op386MOVBload Op386MOVBLSXload Op386MOVWload Op386MOVWLSXload Op386MOVLload Op386MOVBstore Op386MOVWstore Op386MOVLstore Op386MOVBloadidx1 Op386MOVWloadidx1 Op386MOVWloadidx2 Op386MOVLloadidx1 Op386MOVLloadidx4 Op386MOVBstoreidx1 Op386MOVWstoreidx1 Op386MOVWstoreidx2 Op386MOVLstoreidx1 Op386MOVLstoreidx4 Op386MOVBstoreconst Op386MOVWstoreconst Op386MOVLstoreconst Op386MOVBstoreconstidx1 Op386MOVWstoreconstidx1 Op386MOVWstoreconstidx2 Op386MOVLstoreconstidx1 Op386MOVLstoreconstidx4 Op386DUFFZERO Op386REPSTOSL Op386CALLstatic Op386CALLclosure Op386CALLdefer Op386CALLgo Op386CALLinter Op386DUFFCOPY Op386REPMOVSL Op386InvertFlags Op386LoweredGetG Op386LoweredGetClosurePtr Op386LoweredNilCheck Op386MOVLconvert Op386FlagEQ Op386FlagLT_ULT Op386FlagLT_UGT Op386FlagGT_UGT Op386FlagGT_ULT Op386FCHS Op386MOVSSconst1 Op386MOVSDconst1 Op386MOVSSconst2 Op386MOVSDconst2 OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULW OpAMD64HMULB OpAMD64HMULQU OpAMD64HMULLU OpAMD64HMULWU OpAMD64HMULBU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSFW OpAMD64BSRQ OpAMD64BSRL OpAMD64BSRW OpAMD64CMOVQEQconst OpAMD64CMOVLEQconst OpAMD64CMOVWEQconst OpAMD64CMOVQNEconst OpAMD64CMOVLNEconst OpAMD64CMOVWNEconst OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64SQRTSD OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64PXOR OpAMD64LEAQ OpAMD64LEAQ1 OpAMD64LEAQ2 OpAMD64LEAQ4 OpAMD64LEAQ8 OpAMD64LEAL OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64MOVOconst OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLclosure OpAMD64CALLdefer OpAMD64CALLgo OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredNilCheck OpAMD64MOVQconvert OpAMD64MOVLconvert OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMDIV OpARMDIVU OpARMMOD OpARMMODU OpARMADDS OpARMADDSconst OpARMADC OpARMADCconst OpARMSUBS OpARMSUBSconst OpARMRSBSconst OpARMSBC OpARMSBCconst OpARMRSCconst OpARMMULLU OpARMMULA OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMDIVF OpARMDIVD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMMVN OpARMNEGF OpARMNEGD OpARMSQRTD OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRRconst OpARMADDshiftLL OpARMADDshiftRL OpARMADDshiftRA OpARMSUBshiftLL OpARMSUBshiftRL OpARMSUBshiftRA OpARMRSBshiftLL OpARMRSBshiftRL OpARMRSBshiftRA OpARMANDshiftLL OpARMANDshiftRL OpARMANDshiftRA OpARMORshiftLL OpARMORshiftRL OpARMORshiftRA OpARMXORshiftLL OpARMXORshiftRL OpARMXORshiftRA OpARMBICshiftLL OpARMBICshiftRL OpARMBICshiftRA OpARMMVNshiftLL OpARMMVNshiftRL OpARMMVNshiftRA OpARMADCshiftLL OpARMADCshiftRL OpARMADCshiftRA OpARMSBCshiftLL OpARMSBCshiftRL OpARMSBCshiftRA OpARMRSCshiftLL OpARMRSCshiftRL OpARMRSCshiftRA OpARMADDSshiftLL OpARMADDSshiftRL OpARMADDSshiftRA OpARMSUBSshiftLL OpARMSUBSshiftRL OpARMSUBSshiftRA OpARMRSBSshiftLL OpARMRSBSshiftRL OpARMRSBSshiftRA OpARMADDshiftLLreg OpARMADDshiftRLreg OpARMADDshiftRAreg OpARMSUBshiftLLreg OpARMSUBshiftRLreg OpARMSUBshiftRAreg OpARMRSBshiftLLreg OpARMRSBshiftRLreg OpARMRSBshiftRAreg OpARMANDshiftLLreg OpARMANDshiftRLreg OpARMANDshiftRAreg OpARMORshiftLLreg OpARMORshiftRLreg OpARMORshiftRAreg OpARMXORshiftLLreg OpARMXORshiftRLreg OpARMXORshiftRAreg OpARMBICshiftLLreg OpARMBICshiftRLreg OpARMBICshiftRAreg OpARMMVNshiftLLreg OpARMMVNshiftRLreg OpARMMVNshiftRAreg OpARMADCshiftLLreg OpARMADCshiftRLreg OpARMADCshiftRAreg OpARMSBCshiftLLreg OpARMSBCshiftRLreg OpARMSBCshiftRAreg OpARMRSCshiftLLreg OpARMRSCshiftRLreg OpARMRSCshiftRAreg OpARMADDSshiftLLreg OpARMADDSshiftRLreg OpARMADDSshiftRAreg OpARMSUBSshiftLLreg OpARMSUBSshiftRLreg OpARMSUBSshiftRAreg OpARMRSBSshiftLLreg OpARMRSBSshiftRLreg OpARMRSBSshiftRAreg OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMCMPshiftLL OpARMCMPshiftRL OpARMCMPshiftRA OpARMCMPshiftLLreg OpARMCMPshiftRLreg OpARMCMPshiftRAreg OpARMCMPF0 OpARMCMPD0 OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVWloadidx OpARMMOVWloadshiftLL OpARMMOVWloadshiftRL OpARMMOVWloadshiftRA OpARMMOVWstoreidx OpARMMOVWstoreshiftLL OpARMMOVWstoreshiftRL OpARMMOVWstoreshiftRA OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWreg OpARMMOVWnop OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCMOVWHSconst OpARMCMOVWLSconst OpARMSRAcond OpARMCALLstatic OpARMCALLclosure OpARMCALLdefer OpARMCALLgo OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMMOVWconvert OpARMFlagEQ OpARMFlagLT_ULT OpARMFlagLT_UGT OpARMFlagGT_UGT OpARMFlagGT_ULT OpARMInvertFlags OpARM64ADD OpARM64ADDconst OpARM64SUB OpARM64SUBconst OpARM64MUL OpARM64MULW OpARM64MULH OpARM64UMULH OpARM64MULL OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW OpARM64UDIVW OpARM64MOD OpARM64UMOD OpARM64MODW OpARM64UMODW OpARM64FADDS OpARM64FADDD OpARM64FSUBS OpARM64FSUBD OpARM64FMULS OpARM64FMULD OpARM64FDIVS OpARM64FDIVD OpARM64AND OpARM64ANDconst OpARM64OR OpARM64ORconst OpARM64XOR OpARM64XORconst OpARM64BIC OpARM64BICconst OpARM64MVN OpARM64NEG OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD OpARM64SLL OpARM64SLLconst OpARM64SRL OpARM64SRLconst OpARM64SRA OpARM64SRAconst OpARM64RORconst OpARM64RORWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW OpARM64CMPWconst OpARM64CMN OpARM64CMNconst OpARM64CMNW OpARM64CMNWconst OpARM64FCMPS OpARM64FCMPD OpARM64ADDshiftLL OpARM64ADDshiftRL OpARM64ADDshiftRA OpARM64SUBshiftLL OpARM64SUBshiftRL OpARM64SUBshiftRA OpARM64ANDshiftLL OpARM64ANDshiftRL OpARM64ANDshiftRA OpARM64ORshiftLL OpARM64ORshiftRL OpARM64ORshiftRA OpARM64XORshiftLL OpARM64XORshiftRL OpARM64XORshiftRA OpARM64BICshiftLL OpARM64BICshiftRL OpARM64BICshiftRA OpARM64CMPshiftLL OpARM64CMPshiftRL OpARM64CMPshiftRA OpARM64MOVDconst OpARM64FMOVSconst OpARM64FMOVDconst OpARM64MOVDaddr OpARM64MOVBload OpARM64MOVBUload OpARM64MOVHload OpARM64MOVHUload OpARM64MOVWload OpARM64MOVWUload OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload OpARM64MOVBstore OpARM64MOVHstore OpARM64MOVWstore OpARM64MOVDstore OpARM64FMOVSstore OpARM64FMOVDstore OpARM64MOVBstorezero OpARM64MOVHstorezero OpARM64MOVWstorezero OpARM64MOVDstorezero OpARM64MOVBreg OpARM64MOVBUreg OpARM64MOVHreg OpARM64MOVHUreg OpARM64MOVWreg OpARM64MOVWUreg OpARM64MOVDreg OpARM64MOVDnop OpARM64SCVTFWS OpARM64SCVTFWD OpARM64UCVTFWS OpARM64UCVTFWD OpARM64SCVTFS OpARM64SCVTFD OpARM64UCVTFS OpARM64UCVTFD OpARM64FCVTZSSW OpARM64FCVTZSDW OpARM64FCVTZUSW OpARM64FCVTZUDW OpARM64FCVTZSS OpARM64FCVTZSD OpARM64FCVTZUS OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS OpARM64CSELULT OpARM64CSELULT0 OpARM64CALLstatic OpARM64CALLclosure OpARM64CALLdefer OpARM64CALLgo OpARM64CALLinter OpARM64LoweredNilCheck OpARM64Equal OpARM64NotEqual OpARM64LessThan OpARM64LessEqual OpARM64GreaterThan OpARM64GreaterEqual OpARM64LessThanU OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU OpARM64DUFFZERO OpARM64LoweredZero OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64MOVDconvert OpARM64FlagEQ OpARM64FlagLT_ULT OpARM64FlagLT_UGT OpARM64FlagGT_UGT OpARM64FlagGT_ULT OpARM64InvertFlags OpPPC64ADD OpPPC64ADDconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64FSUB OpPPC64FSUBS OpPPC64MULLD OpPPC64MULLW OpPPC64MULHD OpPPC64MULHW OpPPC64MULHDU OpPPC64MULHWU OpPPC64FMUL OpPPC64FMULS OpPPC64SRAD OpPPC64SRAW OpPPC64SRD OpPPC64SRW OpPPC64SLD OpPPC64SLW OpPPC64ADDconstForCarry OpPPC64MaskIfNotCarry OpPPC64SRADconst OpPPC64SRAWconst OpPPC64SRDconst OpPPC64SRWconst OpPPC64SLDconst OpPPC64SLWconst OpPPC64FDIV OpPPC64FDIVS OpPPC64DIVD OpPPC64DIVW OpPPC64DIVDU OpPPC64DIVWU OpPPC64FCTIDZ OpPPC64FCTIWZ OpPPC64FCFID OpPPC64FRSP OpPPC64Xf2i64 OpPPC64Xi2f64 OpPPC64AND OpPPC64ANDN OpPPC64OR OpPPC64ORN OpPPC64XOR OpPPC64EQV OpPPC64NEG OpPPC64FNEG OpPPC64FSQRT OpPPC64FSQRTS OpPPC64ORconst OpPPC64XORconst OpPPC64ANDconst OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBload OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstorezero OpPPC64MOVHstorezero OpPPC64MOVWstorezero OpPPC64MOVDstorezero OpPPC64MOVDaddr OpPPC64MOVDconst OpPPC64MOVWconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CMPUconst OpPPC64CMPWconst OpPPC64CMPWUconst OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64FLessThan OpPPC64LessEqual OpPPC64FLessEqual OpPPC64GreaterThan OpPPC64FGreaterThan OpPPC64GreaterEqual OpPPC64FGreaterEqual OpPPC64LoweredGetClosurePtr OpPPC64LoweredNilCheck OpPPC64MOVDconvert OpPPC64CALLstatic OpPPC64CALLclosure OpPPC64CALLdefer OpPPC64CALLgo OpPPC64CALLinter OpPPC64LoweredZero OpPPC64LoweredMove OpPPC64InvertFlags OpPPC64FlagEQ OpPPC64FlagLT OpPPC64FlagGT OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul8 OpHmul8u OpHmul16 OpHmul16u OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpLrot8 OpLrot16 OpLrot32 OpLrot64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpGreater8 OpGreater8U OpGreater16 OpGreater16U OpGreater32 OpGreater32U OpGreater64 OpGreater64U OpGreater32F OpGreater64F OpGeq8 OpGeq8U OpGeq16 OpGeq16U OpGeq32 OpGeq32U OpGeq64 OpGeq64U OpGeq32F OpGeq64F OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz16 OpCtz32 OpCtz64 OpClz16 OpClz32 OpClz64 OpBswap32 OpBswap64 OpSqrt OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpAddr OpSP OpSB OpFunc OpLoad OpStore OpMove OpZero OpClosureCall OpStaticCall OpDeferCall OpGoCall OpInterCall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpArrayIndex OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake0 OpStructMake1 OpStructMake2 OpStructMake3 OpStructMake4 OpStructSelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarKill OpVarLive OpKeepAlive OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpMul32uhilo OpSignmask OpZeromask OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpSelect0 OpSelect1 ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, clobbers: 32768, // X7 outputs: []outputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, clobbers: 32768, // X7 outputs: []outputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, clobbers: 32768, // X7 outputs: []outputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, clobbers: 32768, // X7 outputs: []outputInfo{ {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 0}, {1, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 0}, {1, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCL", argLen: 3, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLcarry", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 0}, {1, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 0}, {1, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBL", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULW", argLen: 2, clobberFlags: true, asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULB", argLen: 2, clobberFlags: true, asm: x86.AIMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULWU", argLen: 2, clobberFlags: true, asm: x86.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULBU", argLen: 2, clobberFlags: true, asm: x86.AMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MULLQU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "DIVL", argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVW", argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "MODL", argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODW", argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "TESTL", argLen: 2, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTW", argLen: 2, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTB", argLen: 2, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSX", argLen: 1, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSX", argLen: 1, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "REPSTOSL", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 194, // CX SI DI }, }, { name: "REPMOVSL", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "MOVLconvert", argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FCHS", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSSconst2", argLen: 1, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst2", argLen: 1, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "ADDQ", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDQconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "HMULQ", argLen: 2, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULW", argLen: 2, clobberFlags: true, asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULB", argLen: 2, clobberFlags: true, asm: x86.AIMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULQU", argLen: 2, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULWU", argLen: 2, clobberFlags: true, asm: x86.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULBU", argLen: 2, clobberFlags: true, asm: x86.AMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "DIVQ", argLen: 2, clobberFlags: true, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVL", argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVW", argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVQU", argLen: 2, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPQconst", auxType: auxInt64, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "TESTQ", argLen: 2, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTL", argLen: 2, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTW", argLen: 2, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTB", argLen: 2, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTQconst", auxType: auxInt64, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFQ", argLen: 1, clobberFlags: true, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRQ", argLen: 1, clobberFlags: true, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVQEQconst", auxType: auxInt64, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVLEQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVWEQconst", auxType: auxInt16, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVQNEconst", auxType: auxInt64, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVLNEconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVWNEconst", auxType: auxInt16, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVLQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 65536}, // X0 }, clobbers: 128, // DI }, }, { name: "MOVOconst", auxType: auxInt128, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "REPSTOSQ", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 65728, // SI DI X0 }, }, { name: "REPMOVSQ", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQconvert", argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLconvert", argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 14335}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DIV", argLen: 2, clobberFlags: true, asm: arm.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DIVU", argLen: 2, clobberFlags: true, asm: arm.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOD", argLen: 2, clobberFlags: true, asm: arm.AMOD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MODU", argLen: 2, clobberFlags: true, asm: arm.AMODU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCconst", auxType: auxInt32, argLen: 2, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCconst", auxType: auxInt32, argLen: 2, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCconst", auxType: auxInt32, argLen: 2, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "NEGF", argLen: 1, asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NEGD", argLen: 1, asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftLL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftRL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftRA", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftLLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftRLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDshiftRAreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftLLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftRLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORshiftRAreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftLLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftRLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORshiftRAreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftLLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftRLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICshiftRAreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftLLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftRLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVNshiftRAreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftLLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftRLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADCshiftRAreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftLLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftRLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBCshiftRAreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftLLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftRLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSCshiftRAreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDSshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBSshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBSshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 0}, {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMN", argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMPshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMPshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "CMPshiftLLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMPshiftRLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMPshiftRAreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMPF0", argLen: 1, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD0", argLen: 1, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294975488}, // SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWloadshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWloadshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWloadshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVWstoreshiftLL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVWstoreshiftRL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVWstoreshiftRA", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMOVWHSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMOVWLSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRAcond", argLen: 3, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP }, clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredNilCheck", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 2, // R1 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 7, // R0 R1 R2 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 4, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 128}, // R7 }, }, }, { name: "MOVWconvert", argLen: 2, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []outputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUB", argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUBconst", auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UMULH", argLen: 2, commutative: true, asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MULL", argLen: 2, commutative: true, asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UMULL", argLen: 2, commutative: true, asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "DIV", argLen: 2, asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UDIV", argLen: 2, asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "DIVW", argLen: 2, asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UDIVW", argLen: 2, asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOD", argLen: 2, asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MODW", argLen: 2, asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "UMODW", argLen: 2, asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FSUBS", argLen: 2, asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FSUBD", argLen: 2, asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FDIVS", argLen: 2, asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FDIVD", argLen: 2, asm: arm64.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BIC", argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BICconst", auxType: auxInt64, argLen: 1, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MVN", argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "NEG", argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FNEGS", argLen: 1, asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "SLL", argLen: 2, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SRL", argLen: 2, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SRA", argLen: 2, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "RORconst", auxType: auxInt64, argLen: 1, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "RORWconst", auxType: auxInt64, argLen: 1, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMPW", argLen: 2, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMN", argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMNconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMNW", argLen: 2, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMNWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "FCMPS", argLen: 2, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "ADDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ADDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ADDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUBshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUBshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUBshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ANDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ANDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ANDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BICshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BICshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BICshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "CMPshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMPshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "CMPshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FMOVSconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018964258816}, // SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVWUreg", argLen: 1, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVDreg", argLen: 1, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SCVTFWS", argLen: 1, asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "SCVTFWD", argLen: 1, asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "UCVTFWS", argLen: 1, asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "UCVTFWD", argLen: 1, asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "SCVTFS", argLen: 1, asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "SCVTFD", argLen: 1, asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "UCVTFS", argLen: 1, asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "UCVTFD", argLen: 1, asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FCVTZSSW", argLen: 1, asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZSDW", argLen: 1, asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZUSW", argLen: 1, asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZUDW", argLen: 1, asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZSS", argLen: 1, asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZSD", argLen: 1, asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZUS", argLen: 1, asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTZUD", argLen: 1, asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FCVTSD", argLen: 1, asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "FCVTDS", argLen: 1, asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, }, { name: "CSELULT", argLen: 3, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "CSELULT0", argLen: 2, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {1, 67108864}, // R26 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 SP }, clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, }, { name: "LoweredNilCheck", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, clobbers: 65536, // R16 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R16 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, clobbers: 65536, // R16 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R17 {1, 65536}, // R16 {2, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, clobbers: 196608, // R16 R17 }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 67108864}, // R26 }, }, }, { name: "MOVDconvert", argLen: 2, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxSymOff, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHD", argLen: 2, commutative: true, asm: ppc64.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHW", argLen: 2, commutative: true, asm: ppc64.AMULHW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, asm: ppc64.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHWU", argLen: 2, commutative: true, asm: ppc64.AMULHWU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "SRAD", argLen: 2, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAW", argLen: 2, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRD", argLen: 2, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRW", argLen: 2, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLD", argLen: 2, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconstForCarry", auxType: auxInt16, argLen: 1, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 1073741824, // R31 }, }, { name: "MaskIfNotCarry", argLen: 1, asm: ppc64.AADDME, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRADconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "DIVD", argLen: 2, asm: ppc64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVW", argLen: 2, asm: ppc64.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVDU", argLen: 2, asm: ppc64.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVWU", argLen: 2, asm: ppc64.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FCTIDZ", argLen: 1, asm: ppc64.AFCTIDZ, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FCTIWZ", argLen: 1, asm: ppc64.AFCTIWZ, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FCFID", argLen: 1, asm: ppc64.AFCFID, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FRSP", argLen: 1, asm: ppc64.AFRSP, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "Xf2i64", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Xi2f64", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDN", argLen: 2, asm: ppc64.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORN", argLen: 2, asm: ppc64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EQV", argLen: 2, commutative: true, asm: ppc64.AEQV, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FNEG", argLen: 1, asm: ppc64.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FSQRT", argLen: 1, asm: ppc64.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FSQRTS", argLen: 1, asm: ppc64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", argLen: 2, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMOVSload", argLen: 2, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 3}, // SP SB }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: ppc64.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPUconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 1024}, // R11 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 1073741824, // R31 }, }, { name: "MOVDconvert", argLen: 2, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230372393611260, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {1, 1024}, // R11 {0, 536866813}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 288230372393611260, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230372393611260, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 288230372393611260, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 288230372393611260, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R3 {1, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 4, // R3 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R3 {1, 8}, // R4 {2, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 12, // R3 R4 }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, generic: true, }, { name: "Add64F", argLen: 2, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, generic: true, }, { name: "Mul64F", argLen: 2, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul8", argLen: 2, generic: true, }, { name: "Hmul8u", argLen: 2, generic: true, }, { name: "Hmul16", argLen: 2, generic: true, }, { name: "Hmul16u", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, generic: true, }, { name: "Hmul32u", argLen: 2, generic: true, }, { name: "Hmul64", argLen: 2, generic: true, }, { name: "Hmul64u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", argLen: 2, generic: true, }, { name: "Lsh8x16", argLen: 2, generic: true, }, { name: "Lsh8x32", argLen: 2, generic: true, }, { name: "Lsh8x64", argLen: 2, generic: true, }, { name: "Lsh16x8", argLen: 2, generic: true, }, { name: "Lsh16x16", argLen: 2, generic: true, }, { name: "Lsh16x32", argLen: 2, generic: true, }, { name: "Lsh16x64", argLen: 2, generic: true, }, { name: "Lsh32x8", argLen: 2, generic: true, }, { name: "Lsh32x16", argLen: 2, generic: true, }, { name: "Lsh32x32", argLen: 2, generic: true, }, { name: "Lsh32x64", argLen: 2, generic: true, }, { name: "Lsh64x8", argLen: 2, generic: true, }, { name: "Lsh64x16", argLen: 2, generic: true, }, { name: "Lsh64x32", argLen: 2, generic: true, }, { name: "Lsh64x64", argLen: 2, generic: true, }, { name: "Rsh8x8", argLen: 2, generic: true, }, { name: "Rsh8x16", argLen: 2, generic: true, }, { name: "Rsh8x32", argLen: 2, generic: true, }, { name: "Rsh8x64", argLen: 2, generic: true, }, { name: "Rsh16x8", argLen: 2, generic: true, }, { name: "Rsh16x16", argLen: 2, generic: true, }, { name: "Rsh16x32", argLen: 2, generic: true, }, { name: "Rsh16x64", argLen: 2, generic: true, }, { name: "Rsh32x8", argLen: 2, generic: true, }, { name: "Rsh32x16", argLen: 2, generic: true, }, { name: "Rsh32x32", argLen: 2, generic: true, }, { name: "Rsh32x64", argLen: 2, generic: true, }, { name: "Rsh64x8", argLen: 2, generic: true, }, { name: "Rsh64x16", argLen: 2, generic: true, }, { name: "Rsh64x32", argLen: 2, generic: true, }, { name: "Rsh64x64", argLen: 2, generic: true, }, { name: "Rsh8Ux8", argLen: 2, generic: true, }, { name: "Rsh8Ux16", argLen: 2, generic: true, }, { name: "Rsh8Ux32", argLen: 2, generic: true, }, { name: "Rsh8Ux64", argLen: 2, generic: true, }, { name: "Rsh16Ux8", argLen: 2, generic: true, }, { name: "Rsh16Ux16", argLen: 2, generic: true, }, { name: "Rsh16Ux32", argLen: 2, generic: true, }, { name: "Rsh16Ux64", argLen: 2, generic: true, }, { name: "Rsh32Ux8", argLen: 2, generic: true, }, { name: "Rsh32Ux16", argLen: 2, generic: true, }, { name: "Rsh32Ux32", argLen: 2, generic: true, }, { name: "Rsh32Ux64", argLen: 2, generic: true, }, { name: "Rsh64Ux8", argLen: 2, generic: true, }, { name: "Rsh64Ux16", argLen: 2, generic: true, }, { name: "Rsh64Ux32", argLen: 2, generic: true, }, { name: "Rsh64Ux64", argLen: 2, generic: true, }, { name: "Lrot8", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot16", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot32", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot64", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, generic: true, }, { name: "Eq64F", argLen: 2, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, generic: true, }, { name: "Neq64F", argLen: 2, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "Greater8", argLen: 2, generic: true, }, { name: "Greater8U", argLen: 2, generic: true, }, { name: "Greater16", argLen: 2, generic: true, }, { name: "Greater16U", argLen: 2, generic: true, }, { name: "Greater32", argLen: 2, generic: true, }, { name: "Greater32U", argLen: 2, generic: true, }, { name: "Greater64", argLen: 2, generic: true, }, { name: "Greater64U", argLen: 2, generic: true, }, { name: "Greater32F", argLen: 2, generic: true, }, { name: "Greater64F", argLen: 2, generic: true, }, { name: "Geq8", argLen: 2, generic: true, }, { name: "Geq8U", argLen: 2, generic: true, }, { name: "Geq16", argLen: 2, generic: true, }, { name: "Geq16U", argLen: 2, generic: true, }, { name: "Geq32", argLen: 2, generic: true, }, { name: "Geq32U", argLen: 2, generic: true, }, { name: "Geq64", argLen: 2, generic: true, }, { name: "Geq64U", argLen: 2, generic: true, }, { name: "Geq32F", argLen: 2, generic: true, }, { name: "Geq64F", argLen: 2, generic: true, }, { name: "AndB", argLen: 2, generic: true, }, { name: "OrB", argLen: 2, generic: true, }, { name: "EqB", argLen: 2, generic: true, }, { name: "NeqB", argLen: 2, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Clz16", argLen: 1, generic: true, }, { name: "Clz32", argLen: 1, generic: true, }, { name: "Clz64", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Phi", argLen: -1, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, generic: true, }, { name: "SP", argLen: 0, generic: true, }, { name: "SB", argLen: 0, generic: true, }, { name: "Func", auxType: auxSym, argLen: 0, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Store", auxType: auxInt64, argLen: 3, generic: true, }, { name: "Move", auxType: auxInt64, argLen: 3, generic: true, }, { name: "Zero", auxType: auxInt64, argLen: 2, generic: true, }, { name: "ClosureCall", auxType: auxInt64, argLen: 3, generic: true, }, { name: "StaticCall", auxType: auxSymOff, argLen: 1, generic: true, }, { name: "DeferCall", auxType: auxInt64, argLen: 1, generic: true, }, { name: "GoCall", auxType: auxInt64, argLen: 1, generic: true, }, { name: "InterCall", auxType: auxInt64, argLen: 2, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, generic: true, }, { name: "GetG", argLen: 1, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "ArrayIndex", auxType: auxInt64, argLen: 1, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake0", argLen: 0, generic: true, }, { name: "StructMake1", argLen: 1, generic: true, }, { name: "StructMake2", argLen: 2, generic: true, }, { name: "StructMake3", argLen: 3, generic: true, }, { name: "StructMake4", argLen: 4, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, generic: true, }, { name: "VarKill", auxType: auxSym, argLen: 1, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, generic: true, }, { name: "KeepAlive", argLen: 2, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Mul32uhilo", argLen: 2, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, generic: true, }, { name: "Select1", argLen: 1, generic: true, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) String() string { return opcodeTable[o].name } var registers386 = [...]Register{ {0, "AX"}, {1, "CX"}, {2, "DX"}, {3, "BX"}, {4, "SP"}, {5, "BP"}, {6, "SI"}, {7, "DI"}, {8, "X0"}, {9, "X1"}, {10, "X2"}, {11, "X3"}, {12, "X4"}, {13, "X5"}, {14, "X6"}, {15, "X7"}, {16, "SB"}, } var gpRegMask386 = regMask(239) var fpRegMask386 = regMask(65280) var framepointerReg386 = int8(5) var registersAMD64 = [...]Register{ {0, "AX"}, {1, "CX"}, {2, "DX"}, {3, "BX"}, {4, "SP"}, {5, "BP"}, {6, "SI"}, {7, "DI"}, {8, "R8"}, {9, "R9"}, {10, "R10"}, {11, "R11"}, {12, "R12"}, {13, "R13"}, {14, "R14"}, {15, "R15"}, {16, "X0"}, {17, "X1"}, {18, "X2"}, {19, "X3"}, {20, "X4"}, {21, "X5"}, {22, "X6"}, {23, "X7"}, {24, "X8"}, {25, "X9"}, {26, "X10"}, {27, "X11"}, {28, "X12"}, {29, "X13"}, {30, "X14"}, {31, "X15"}, {32, "SB"}, } var gpRegMaskAMD64 = regMask(65519) var fpRegMaskAMD64 = regMask(4294901760) var framepointerRegAMD64 = int8(5) var registersARM = [...]Register{ {0, "R0"}, {1, "R1"}, {2, "R2"}, {3, "R3"}, {4, "R4"}, {5, "R5"}, {6, "R6"}, {7, "R7"}, {8, "R8"}, {9, "R9"}, {10, "g"}, {11, "R11"}, {12, "R12"}, {13, "SP"}, {14, "R14"}, {15, "R15"}, {16, "F0"}, {17, "F1"}, {18, "F2"}, {19, "F3"}, {20, "F4"}, {21, "F5"}, {22, "F6"}, {23, "F7"}, {24, "F8"}, {25, "F9"}, {26, "F10"}, {27, "F11"}, {28, "F12"}, {29, "F13"}, {30, "F14"}, {31, "F15"}, {32, "SB"}, } var gpRegMaskARM = regMask(5119) var fpRegMaskARM = regMask(4294901760) var framepointerRegARM = int8(-1) var registersARM64 = [...]Register{ {0, "R0"}, {1, "R1"}, {2, "R2"}, {3, "R3"}, {4, "R4"}, {5, "R5"}, {6, "R6"}, {7, "R7"}, {8, "R8"}, {9, "R9"}, {10, "R10"}, {11, "R11"}, {12, "R12"}, {13, "R13"}, {14, "R14"}, {15, "R15"}, {16, "R16"}, {17, "R17"}, {18, "R18"}, {19, "R19"}, {20, "R20"}, {21, "R21"}, {22, "R22"}, {23, "R23"}, {24, "R24"}, {25, "R25"}, {26, "R26"}, {27, "g"}, {28, "R29"}, {29, "SP"}, {30, "F0"}, {31, "F1"}, {32, "F2"}, {33, "F3"}, {34, "F4"}, {35, "F5"}, {36, "F6"}, {37, "F7"}, {38, "F8"}, {39, "F9"}, {40, "F10"}, {41, "F11"}, {42, "F12"}, {43, "F13"}, {44, "F14"}, {45, "F15"}, {46, "F16"}, {47, "F17"}, {48, "F18"}, {49, "F19"}, {50, "F20"}, {51, "F21"}, {52, "F22"}, {53, "F23"}, {54, "F24"}, {55, "F25"}, {56, "F26"}, {57, "F27"}, {58, "F28"}, {59, "F29"}, {60, "F30"}, {61, "F31"}, {62, "SB"}, } var gpRegMaskARM64 = regMask(133955583) var fpRegMaskARM64 = regMask(288230375077969920) var framepointerRegARM64 = int8(-1) var registersPPC64 = [...]Register{ {0, "SP"}, {1, "SB"}, {2, "R3"}, {3, "R4"}, {4, "R5"}, {5, "R6"}, {6, "R7"}, {7, "R8"}, {8, "R9"}, {9, "R10"}, {10, "R11"}, {11, "R12"}, {12, "R13"}, {13, "R14"}, {14, "R15"}, {15, "R16"}, {16, "R17"}, {17, "R18"}, {18, "R19"}, {19, "R20"}, {20, "R21"}, {21, "R22"}, {22, "R23"}, {23, "R24"}, {24, "R25"}, {25, "R26"}, {26, "R27"}, {27, "R28"}, {28, "R29"}, {29, "g"}, {30, "R31"}, {31, "F0"}, {32, "F1"}, {33, "F2"}, {34, "F3"}, {35, "F4"}, {36, "F5"}, {37, "F6"}, {38, "F7"}, {39, "F8"}, {40, "F9"}, {41, "F10"}, {42, "F11"}, {43, "F12"}, {44, "F13"}, {45, "F14"}, {46, "F15"}, {47, "F16"}, {48, "F17"}, {49, "F18"}, {50, "F19"}, {51, "F20"}, {52, "F21"}, {53, "F22"}, {54, "F23"}, {55, "F24"}, {56, "F25"}, {57, "F26"}, } var gpRegMaskPPC64 = regMask(536866812) var fpRegMaskPPC64 = regMask(288230371856744448) var framepointerRegPPC64 = int8(0)