From 818c5f6fbe136286b7c76f38a11929a60eb327bc Mon Sep 17 00:00:00 2001 From: Cherry Zhang Date: Fri, 28 Jun 2019 09:30:36 -0400 Subject: [release-branch.go1.15] cmd/compile: mark R16, R17 clobbered for non-standard calls on ARM64 On ARM64, (external) linker generated trampoline may clobber R16 and R17. In CL 183842 we change Duff's devices not to use those registers. However, this is not enough. The register allocator also needs to know that these registers may be clobbered in any calls that don't follow the standard Go calling convention. This include Duff's devices and the write barrier. Fixes #46927. Updates #32773. Change-Id: Ia52a891d9bbb8515c927617dd53aee5af5bd9aa4 Reviewed-on: https://go-review.googlesource.com/c/go/+/184437 Run-TryBot: Cherry Zhang TryBot-Result: Go Bot Reviewed-by: Meng Zhuo Reviewed-by: Keith Randall Trust: Meng Zhuo (cherry picked from commit 11b4aee05bfe83513cf08f83091e5aef8b33e766) Reviewed-on: https://go-review.googlesource.com/c/go/+/331030 Trust: Cherry Mui Run-TryBot: Cherry Mui --- src/cmd/compile/internal/ssa/gen/ARM64Ops.go | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/cmd/compile/internal/ssa/gen/ARM64Ops.go') diff --git a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go index b402e35ea6..2208d26df9 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go +++ b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go @@ -498,13 +498,14 @@ func init() { // auxint = offset into duffzero code to start executing // returns mem // R20 changed as side effect + // R16 and R17 may be clobbered by linker trampoline. { name: "DUFFZERO", aux: "Int64", argLength: 2, reg: regInfo{ inputs: []regMask{buildReg("R20")}, - clobbers: buildReg("R20 R30"), + clobbers: buildReg("R16 R17 R20 R30"), }, faultOnNilArg0: true, }, @@ -537,13 +538,14 @@ func init() { // auxint = offset into duffcopy code to start executing // returns mem // R20, R21 changed as side effect + // R16 and R17 may be clobbered by linker trampoline. { name: "DUFFCOPY", aux: "Int64", argLength: 3, reg: regInfo{ inputs: []regMask{buildReg("R21"), buildReg("R20")}, - clobbers: buildReg("R20 R21 R26 R30"), + clobbers: buildReg("R16 R17 R20 R21 R26 R30"), }, faultOnNilArg0: true, faultOnNilArg1: true, @@ -664,7 +666,8 @@ func init() { // LoweredWB invokes runtime.gcWriteBarrier. arg0=destptr, arg1=srcptr, arg2=mem, aux=runtime.gcWriteBarrier // It saves all GP registers if necessary, // but clobbers R30 (LR) because it's a call. - {name: "LoweredWB", argLength: 3, reg: regInfo{inputs: []regMask{buildReg("R2"), buildReg("R3")}, clobbers: (callerSave &^ gpg) | buildReg("R30")}, clobberFlags: true, aux: "Sym", symEffect: "None"}, + // R16 and R17 may be clobbered by linker trampoline. + {name: "LoweredWB", argLength: 3, reg: regInfo{inputs: []regMask{buildReg("R2"), buildReg("R3")}, clobbers: (callerSave &^ gpg) | buildReg("R16 R17 R30")}, clobberFlags: true, aux: "Sym", symEffect: "None"}, // There are three of these functions so that they can have three different register inputs. // When we check 0 <= c <= cap (A), then 0 <= b <= c (B), then 0 <= a <= b (C), we want the -- cgit v1.2.3-54-g00ecf